abstract: In thesis, a test time reduction (a low cost test) methodology for digitally-calibrated pipeline analog-to-digital converters (ADCs) is presented. A long calibration time is required in the final test to validate performance of these designs. To reduce total test time, optimized calibration technique and calibrated effective number of bits (ENOB) prediction from calibration coefficient will be presented. With the prediction technique, failed devices can be identified only without actual calibration. This technique reduces significant amount of time for the total test time. / Dissertation/Thesis / M.S. Electrical Engineering 2013
| Identifer | oai:union.ndltd.org:asu.edu/item:21026 |
| Date | January 2013 |
| Contributors | Kim, Kibeom (Author), Ozev, Sule (Advisor), Kitchen, Jennifer (Committee member), Barnaby, Hugh (Committee member), Arizona State University (Publisher) |
| Source Sets | Arizona State University |
| Language | English |
| Detected Language | English |
| Type | Masters Thesis |
| Format | 31 pages |
| Rights | http://rightsstatements.org/vocab/InC/1.0/, All Rights Reserved |
Page generated in 0.0017 seconds