When VLSI devices are viewed using a Scanning Electron Microscope (SEM) with a low energy (1keV) primary beam, exposed dielectric surfaces can undergo charging. Such charging can have an adverse effect on voltage contrast testing of the device. The aim of this thesis is to improve understanding of charging behaviour. By adopting common VLSI materials and typical voltage contast SEM configurations, it makes a qualitative study of the factors that influence VLSI specimen charging. A model of specimen charging, based on the study, is then formulated and assessed.
| Identifer | oai:union.ndltd.org:bl.uk/oai:ethos.bl.uk:664015 |
| Date | January 1992 |
| Creators | Worlock, Stephen |
| Publisher | University of Edinburgh |
| Source Sets | Ethos UK |
| Detected Language | English |
| Type | Electronic Thesis or Dissertation |
| Source | http://hdl.handle.net/1842/14704 |
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