When VLSI devices are viewed using a Scanning Electron Microscope (SEM) with a low energy (1keV) primary beam, exposed dielectric surfaces can undergo charging. Such charging can have an adverse effect on voltage contrast testing of the device. The aim of this thesis is to improve understanding of charging behaviour. By adopting common VLSI materials and typical voltage contast SEM configurations, it makes a qualitative study of the factors that influence VLSI specimen charging. A model of specimen charging, based on the study, is then formulated and assessed.

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Electron Beam Testing Techniques have gained widespread acceptance throughout the electronics industry in the design verification of prototypes and the failure analysis of production devices. In the past, these techniques have gained little prominence, with the micro-prober being the main tool used during the diagnostic process. The increasing integration of modern semiconductors has resulted in the mechanical prober effectively becoming obsolete due to the capacitive loading that these 1μm probes introduce. The need for an integrated diagnostic system also becomes greater with the increasing complexity of devices. In particular, the tools required to perform a successful analysis include the design database, test stimulus and an electron beam testing system. The most effective way to create the required debug environment is to integrate all the isolated tools involved around a centralised host. This work involves the development of an integrated electron beam test system which meets the specific industrial requirements of a failure analysis facility. This system is based around a workstation which provides complete control of all aspects of the debug environment. A particular problem identified with this system was the susceptibility of the secondary electron detector to local field effects. The design and development of a new electron detector allowed a significant improvement in the quantitative measurement accuracy of the system to be demonstrated. Image processing algorithms were shown to have applications both in the improvement of picture quality and the manipulation of acquired images. A novel approach was introduced for the identification of chosen features on the device. The application of the developed system in the debug of complex VLSI devices is demonstrated with several failure mechanisms being uncovered.

Partial discharge (PD) data has been recorded simultaneously using the conventional IEC60270 `apparent charge' measurement technique and the more recent Radio Frequency (RF) method. Due to the different responses of each system, combined measurement allows additional information on the nature of the PD source to be gained. PD was produced using a number of test cells containing PD sources typically encountered in practical insulation systems, such as free particles, floating electrodes and voids. When RF energy is plotted against apparent charge for a large number of discharges, characteristic patterns appear which may be used to distinguish between PD sources. Additionally, the combined technique has the ability to distinguish between simultaneously active PD sources by the appearance of multiple clusters. Additional work has been carried out to aid in the understanding and interpretation of these relationships. For example, an algorithm that models the complete response of a gas-insulated switchgear chamber has shown that PDs with a consistent pulse width produce correlation patterns that resemble a quadratic relationship. Additionally, direct PD current pulse measurement has shown a large variation in current pulse shape with faster rise times than previously expected (35 ps minimum). It is envisioned that the ability to relate RF measurements to the internationally accepted apparent charge level will aid in the general acceptance of the RF technique as a tool to quantify PD severity.

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