Modern DSP applications present increasingly high computational requirements and keep evolving in nature. Field Programmable Gate Arrays (FPGAs) host a vast array of logic; hardwired DSP slices and memory resources combined with reconfigurability, emerging as a promising platform for DSP implementations. However, the current manner of programming FPGA still relies on design of dedicated circuits which is time consuming and complex. This has prompted the emergence of 'soft' processor architectures, hosted on the FPGAs reconfigurable fabric. However, existing softcore processors are still constrained in terms of performance, resource efficiency and applicability. In this thesis, these issues are addressed by a proposed Softcore Stream Processor (SSP). The SSP is used to achieve the first recorded software defined IEEE 802.11 ac FFT architecture with real-time processing ability for 8 channels and all required bandwidths. More importantly, it demonstrates not only it can offer a flexible, real-time processing, it also achieves reductions in resource cost of, on average, 65%, compared to dedicated circuit designs. Sliding window applications as an important subdomain of DSP applications are also targeted in this thesis. The implementations achieve over an order of magnitude higher resource efficiency when compared to current best metrics achieved by soft vector processors. In addition to the novel softcore architecture, a model-level SSP platform synthesis flow is presented to allow generation of high-quality real-time DSP on SSP in a systematic and automated way.
| Identifer | oai:union.ndltd.org:bl.uk/oai:ethos.bl.uk:677848 |
| Date | January 2014 |
| Creators | Wang, P. |
| Publisher | Queen's University Belfast |
| Source Sets | Ethos UK |
| Detected Language | English |
| Type | Electronic Thesis or Dissertation |
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