This thesis is concerned with challenging the design space of Elliptic Curve Cryptography (ECC) over binary Galois Field, GF(2m) in hardware on field-programmable gate array (FPGA) in terms of area, speed and latency. Novel contributions have been made at the algorithmic, architectural and implementation levels that produced leading performance figures in terms of key hardware implementation metrics on FPGA. This demonstrated performance will enable ECC to be deployed across a range of application requiring public key security using FPGA technology. The proposed low area ECC implementation outperforms relevant state of the art in both area-time and area2-time metrics. The proposed high throughput ECC implementation adopts a new digit serial multiplier over GF(2m) incorporating a novel pipelining technique along with algorithmic and architectural level modification to support parallel operations in the arithmetic level. The resulting throughput/area performance outperforms state of the art designs on FPGA to date. The proposed high-speed only implementation utilises a new full-precision multiplier and smart point multiplication scheduling to reduce the latency. The resulting high speed ECC design with three multipliers achieves the lowest reported latency figure to date with high speed (450 clock cycles to get 2.83 μs on Virtex7). Finally, the proposed low resources scalable ECC implementation is based on very low latency multiprecision multiplication and low latency multiprecision squaring. The scalable ECC point multiplication design over all NIST curves consumes very low latency and shows the best area-time performance on FPGA to date.
| Identifer | oai:union.ndltd.org:bl.uk/oai:ethos.bl.uk:689327 |
| Date | January 2016 |
| Creators | Khan, Zia |
| Contributors | Benaissa, Mohammed |
| Publisher | University of Sheffield |
| Source Sets | Ethos UK |
| Detected Language | English |
| Type | Electronic Thesis or Dissertation |
| Source | http://etheses.whiterose.ac.uk/13516/ |
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