by Yuen Siu Ming. / Thesis (M.Phil.)--Chinese University of Hong Kong, 1995. / Includes bibliographical references (leaves 104-110). / Chapter 1 --- Introduction --- p.1 / Chapter 2 --- Background --- p.4 / Chapter 2.1 --- Approaches in Formal Hardware Verification --- p.4 / Chapter 2.1.1 --- Theorem Proving --- p.5 / Chapter 2.1.2 --- Symbolic Simulation --- p.5 / Chapter 2.1.3 --- Model Checking --- p.6 / Chapter 2.2 --- Temporal Theories --- p.7 / Chapter 2.3 --- Related Works --- p.8 / Chapter 2.3.1 --- Consistency and Satisfiability of Timing Specifications --- p.8 / Chapter 2.3.2 --- Symbolic Constraint Satisfaction --- p.9 / Chapter 3 --- Problem Domain --- p.11 / Chapter 3.1 --- Basics of MC68000 Read Cycle --- p.11 / Chapter 4 --- Knowledge-based System Structure --- p.13 / Chapter 4.1 --- Diagnostic Reasoning Mechanisms --- p.14 / Chapter 4.2 --- Occurring Event Sequence --- p.16 / Chapter 4.3 --- Equivalent Goals --- p.17 / Chapter 4.4 --- CPU Databus Setup Time --- p.17 / Chapter 4.5 --- Assertion of CPU AS Signal --- p.19 / Chapter 5 --- Time Range Approach --- p.21 / Chapter 5.1 --- Time Range Represent ation --- p.21 / Chapter 5.2 --- Time Ranges Reasoning Techniques --- p.22 / Chapter 5.2.1 --- Constraint Satisfaction of Time Ranges --- p.22 / Chapter 5.2.2 --- Constraint Propagation of Time Ranges --- p.25 / Chapter 5.3 --- Worst-Case Timing Analysis --- p.28 / Chapter 5.4 --- System Implementation --- p.29 / Chapter 5.4.1 --- CPU Databus Setup Time --- p.30 / Chapter 5.4.2 --- Assertion of CPU AS Signal --- p.36 / Chapter 5.5 --- Implementation Results --- p.40 / Chapter 5.5.1 --- CPU Databus Setup Time --- p.40 / Chapter 5.5.2 --- Assertion of CPU AS Signal --- p.40 / Chapter 5.6 --- Conclusion --- p.41 / Chapter 6 --- Fuzzy Time Point Approach --- p.43 / Chapter 6.1 --- Fuzzy Time Point Models --- p.44 / Chapter 6.1.1 --- Concept of Fuzzy Numbers --- p.44 / Chapter 6.1.2 --- Definition of Fuzzy Time Points --- p.45 / Chapter 6.1.3 --- Semi-bounded Fuzzy Time Points --- p.47 / Chapter 6.2 --- Fuzzy Time Point Reasoning Techniques --- p.48 / Chapter 6.2.1 --- Constraint Propagation of Fuzzy Time Points --- p.50 / Chapter 6.2.2 --- Constraint Satisfaction of Fuzzy Time Points --- p.52 / Chapter 6.3 --- System Implementation --- p.55 / Chapter 6.3.1 --- Representation of Fuzzy Time Point --- p.55 / Chapter 6.3.2 --- Fuzzy Time Point Satisfaction --- p.56 / Chapter 6.3.3 --- Fuzzy Time Point Propagation --- p.58 / Chapter 6.4 --- Implementation Results --- p.64 / Chapter 6.4.1 --- CPU Databus Setup Time --- p.64 / Chapter 6.4.2 --- Assertion of CPU AS Signal --- p.65 / Chapter 6.5 --- Fuzzy Time Point Model Parameters --- p.66 / Chapter 6.5.1 --- Variation of Semi-bounded ftps' Membership Function --- p.66 / Chapter 6.5.2 --- Variation of μftp --- p.67 / Chapter 6.5.3 --- Variation of K --- p.69 / Chapter 6.6 --- Conclusion --- p.69 / Chapter 7 --- Constraint Compatibility Reasoning --- p.72 / Chapter 7.1 --- Abstract Timing Parameters --- p.73 / Chapter 7.2 --- MC68000 Read Cycle: Wait States Insertion --- p.75 / Chapter 7.3 --- Constraint Compatibility of Fuzzy Time Point --- p.75 / Chapter 7.3.1 --- Crisp Threshold Value --- p.77 / Chapter 7.3.2 --- Possibility Quantification for the Number of Wait States --- p.78 / Chapter 7.3.3 --- Threshold Beyond Fuzzy Time Point --- p.80 / Chapter 7.3.4 --- Fuzzy Time Point Beyond Threshold --- p.80 / Chapter 7.3.5 --- Threshold Within Fuzzy Time Point --- p.82 / Chapter 7.4 --- Determine When CPU Clock State is S5 --- p.83 / Chapter 7.5 --- System Implementation --- p.84 / Chapter 7.5.1 --- Expert's Heuristic Rule --- p.84 / Chapter 7.5.2 --- Constraint Compatibility --- p.85 / Chapter 7.5.3 --- Wait States Insertion --- p.87 / Chapter 7.6 --- Implementation Results --- p.91 / Chapter 7.7 --- Conclusion --- p.93 / Chapter 8 --- Conclusion --- p.95 / Chapter 8.1 --- Applications in Other Domains --- p.97 / Chapter 8.2 --- Future Directions and Recommendations --- p.98 / Chapter A --- Constraint Compatibility Reasoning Output --- p.99 / Chapter A.1 --- No Wait Cycle Insertion --- p.99 / Chapter A.2 --- Single Wait Cycle Insertion --- p.100 / Chapter A.3 --- Two Wait Cycle Insertions --- p.100 / Chapter B --- MC68020 Read Cycle Problem --- p.101 / Chapter B.1 --- Basics of MC68020 Read Cycle --- p.101 / Chapter B.2 --- MC68020 Databus Setup Time --- p.102 / Chapter B.3 --- Implementation Results --- p.103 / Bibliography --- p.104
| Identifer | oai:union.ndltd.org:cuhk.edu.hk/oai:cuhk-dr:cuhk_320585 |
| Date | January 1995 |
| Contributors | Yuen, Siu Ming., Chinese University of Hong Kong Graduate School. Division of Systems Engineering and Engineering Management. |
| Publisher | Chinese University of Hong Kong |
| Source Sets | The Chinese University of Hong Kong |
| Language | English |
| Detected Language | English |
| Type | Text, bibliography |
| Format | print, xi, 104, [6] leaves : ill. ; 30 cm. |
| Rights | Use of this resource is governed by the terms and conditions of the Creative Commons “Attribution-NonCommercial-NoDerivatives 4.0 International” License (http://creativecommons.org/licenses/by-nc-nd/4.0/) |
Page generated in 0.0018 seconds