Memory wall is becoming a more and more serious bottleneck of the processing speed of microprocessors. The mismatch between CPUs and memories has been increasing since three decades ago. SRAM was introduced as the bridge between the main memory and the CPU. SRAM is designed to be on the same die with CPU and stores temporary data and instructions that are to be processed by the CPU. Thus, the performance of SRAMs has a direct impact on the performance of CPUs.
With the application of mass amount data to be processed nowadays, there is a great need for high-performance CPUs. Three dimensional CPUs and CPUs that are specifically designed for machine learning are gaining popularity. The objective of this work is to design high-performance SRAM for these two emerging applications. Firstly, a novel delay cell based on dummy TSV is proposed to replace traditional delay cells for better timing control. Secondly, a unique SRAM with novel architecture is custom designed for a high-performance machine learning processor. Post-layout simulation shows that the SRAM works well with the processing core and its design is optimized to work well with machine learning processors based on convolutional neural networks. A prototype of the SRAM is also tapped out to further verify our design.
| Identifer | oai:union.ndltd.org:ndsu.edu/oai:library.ndsu.edu:10365/31743 |
| Date | January 2018 |
| Creators | Chen, Xiaowei |
| Publisher | North Dakota State University |
| Source Sets | North Dakota State University |
| Detected Language | English |
| Type | text/dissertation |
| Format | application/pdf |
| Rights | NDSU policy 190.6.2, https://www.ndsu.edu/fileadmin/policy/190.pdf |
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