The focus of this thesis is on specialising the configuration of a field-programmable gate array
(FPGA) to allow dynamic reconfiguration of real-time applications. The dynamic reconfiguration
of an application has numerous advantages, but due to the overhead introduced by
this process, it is only advantageous if the execution time exceeds reconfiguration time. This
implies that dynamic reconfiguration is more suited to quasi-static applications, and real-time
applications are therefore typically not reconfigured.
A method proposed in the literature to ameliorate the overhead from the configuration process is
to use a block-RAM (BRAM) based, hardware-controlled reconfiguration architecture, eliminating
the need for a processor bus by storing the configuration in localised memory. The drawback
of this architecture is the limited size of the BRAM, implying only a subset of configurations
can be stored.
The work presented in this thesis aim to address this size limitation by proposing a specialiser
capable of adapting the configuration stored in the BRAM to represent different sets of hardware.
This is done by directly manipulating the bits in the configuration using passive hardware. This
not only allows the configuration to be specialised practically immediately, but also allows this
specialiser to be device independent. By incorporating this specialiser into the BRAM-based
architecture, this study sets out to establish that it is possible to reduce the overhead of the
reconfiguration process to such an extent that dynamic reconfiguration can be used for real-time
applications.
Since the composition of the configuration is not publicly available, a method had to be found to
parse and analyse the configuration in order to map the configuration space of the device. The
approach used was to compare numerous different configurations and mapping the differences.
By analysing these differences, it was found that there is a logical relationship between the slice
coordinates and the configuration space of the device. The encoding of the lookup tables was
also determined from their initialisation parameters. This allows the configuration of any lookup
table to be changed by simply changing the corresponding bits in the configuration.
Using this proposed reconfiguration architecture, a distributed multiply-accumulate was reconi
figured and its functional density measured. The reason for selecting this specific application
is because the multiply-accumulate instruction can be found at the heart of many real-time
applications. If the functional density of the reconfigured application is comparable to those
of its static equivalent, a strong case can be made for real-time reconfiguration in general.
Functional density is an indication of the composite benefits dynamic reconfiguration obtains
above its static generic counterpart. Due to the overhead of the reconfiguration process, the
functional density of reconfigured applications is traditionally significantly lower than those of
static applications. If the functional density of the reconfigured application can rival those of
the static equivalent, the overhead from the reconfiguration process becomes negligible.
Using this metric, the functional density of the distributed multiply-accumulate was compared
for different reconfiguration implementations. It was found that the reconfiguration architecture
proposed in this thesis yields a significant improvement over other reconfiguration methods. In
fact, the functional density of this method rivalled that of its static equivalent, implying that
it is possible to dynamically reconfigure a real-time application. It was also found that the
proposed architecture reduces specialisation and reconfiguration time to such an extent that it
is possible complete the reconfiguration process within strict time constraints. Even though the
proposed method is only capable of reconfiguring the LUTs of a real-time application, this is
the first step towards allowing full reconfiguration of applications with dynamic characteristics.
The first contribution this thesis makes is a novel method to parse and analyse the configuration
of a XilinxR
VirtexR
-5 FPGA. It also successfully maps the configuration space to
the configuration data. Even though this method is applied to a specific device, it is device
independent and can easily be applied to any other FPGA. The second contribution comes from
using the information obtained from this analysis to design and implement a configuration
specialiser, capable of adapting lookup tables in real time. Lastly, the third contribution
combines this specialiser with the BRAM-based architecture to allow the reconfiguration of
applications typically not reconfigured. / PhD (Computer and Electronic Engineering), North-West University, Potchefstroom Campus, 2015
| Identifer | oai:union.ndltd.org:netd.ac.za/oai:union.ndltd.org:nwu/oai:dspace.nwu.ac.za:10394/15358 |
| Date | January 2015 |
| Creators | Le Roux, Ronnie Rikus |
| Source Sets | South African National ETD Portal |
| Language | English |
| Detected Language | English |
| Type | Thesis |
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