Thesis (MScEng (Electrical and Electronic Engineering))--University of Stellenbosch, 2006. / Integrated circuits are expensive to manufacture and it is important to verify the correct
operation of a circuit before fabrication. Efficient, though accurate, parameter extraction
of post-layout designs are required for estimation of circuit success rates. This thesis
discusses electrical netlist and fast parameter extraction techniques suited for both intraand
inter-gate connections. This includes the use of extraction windows and look-up tables
(LUTs) for accurate inductance and capacitance estimation. These techniques can readily
be implemented in automated layout software where fast parameter extraction is required
for timing analysis and gate placement.
| Identifer | oai:union.ndltd.org:netd.ac.za/oai:union.ndltd.org:sun/oai:scholar.sun.ac.za:10019.1/1652 |
| Date | 12 1900 |
| Creators | Lotter, Pierre |
| Contributors | Perold, W. J., University of Stellenbosch. Faculty of Engineering. Dept. of Electrical and Electronic Engineering. |
| Publisher | Stellenbosch : University of Stellenbosch |
| Source Sets | South African National ETD Portal |
| Language | English |
| Detected Language | English |
| Type | Thesis |
| Format | 1408363 bytes, application/pdf |
| Rights | University of Stellenbosch |
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