Approved for public release; distribution is unlimited / The main focus in the design of the next generation combatant, DD(X), is the US Navy's proposed Integrated Power System (IPS) which includes an all-electric propulsion drive system. The reduction of current waveform harmonics is critical in combatant propulsion systems such as the IPS. One method of reducing the current harmonics is to utilize a multilevel converter topology. The multi-level converter, as compared to a standard converter, features low dv/dt losses and low switching losses. This thesis examines the design, construction and testing of two multi-level converters operated in tandem, called a Cascaded Multi-Level Converter (CMLC). A digital logic switching circuit is designed and constructed to control the CMLC during the operational testing phase. The CMLC is demonstrated in a three-phase high-voltage configuration with 178.5 V zero-to-peak voltage, 2.10 A zero-to-peak current achieved using an R-L load. / Lieutenant Commander, United States Navy
| Identifer | oai:union.ndltd.org:nps.edu/oai:calhoun.nps.edu:10945/1006 |
| Date | 06 1900 |
| Creators | Crowe, Robert A. |
| Contributors | Ashton, Robert W., Ciezki, John G., Fouts, Douglas J., Electrical Engineering |
| Publisher | Monterey, California. Naval Postgraduate School |
| Source Sets | Naval Postgraduate School |
| Detected Language | English |
| Type | Thesis |
| Format | xvi, 127 p. : ill. (some col.) ;, application/pdf |
| Rights | This publication is a work of the U.S. Government as defined in Title 17, United States Code, Section 101. As such, it is in the public domain, and under the provisions of Title 17, United States Code, Section 105, may not be copyrighted. |
Page generated in 0.002 seconds