Approved for public release, distribution is unlimited / A hardware interface is designed, developed, constructed, and tested to interface a naval radar to the SRC 6E reconfigurable computer. The U.S. Navy AN/SPS 65 radar provides in-phase (I) and quadrature (Q) channels along with the AGC voltage to the hardware interface in analog form. The hardware interface receives a sampling clock from the SRC 6E and in turn performs the requisite attenuation and digital conversion before presenting the signals to the SRC 6E through its CHAIN port. The results show that the SRC 6E can effectively generate a sampling clock to drive the analog-to-digital converters and that real- time radar data can be brought into the SRC 6E via its high speed CHAIN port for performing high speed digital signal processing. / Lieutenant, United States Naval Reserve
| Identifer | oai:union.ndltd.org:nps.edu/oai:calhoun.nps.edu:10945/2206 |
| Date | 03 1900 |
| Creators | King, Timothy L. |
| Contributors | Fouts, Douglas J., Pace, Phillip E., Naval Postgraduate School (U.S.)., Department of Electrical and Computer Engineering |
| Publisher | Monterey California. Naval Postgraduate School |
| Source Sets | Naval Postgraduate School |
| Detected Language | English |
| Type | Thesis |
| Format | xviii, 107 p. : ill. (some col.), application/pdf |
| Rights | This publication is a work of the U.S. Government as defined in Title 17, United States Code, Section 101. As such, it is in the public domain, and under the provisions of Title 17, United States Code, Section 105, may not be copyrighted. |
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