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Approved for public release, distribution is unlimited / A hardware interface is designed, developed, constructed, and tested to interface a naval radar to the SRC 6E reconfigurable computer. The U.S. Navy AN/SPS 65 radar provides in-phase (I) and quadrature (Q) channels along with the AGC voltage to the hardware interface in analog form. The hardware interface receives a sampling clock from the SRC 6E and in turn performs the requisite attenuation and digital conversion before presenting the signals to the SRC 6E through its CHAIN port. The results show that the SRC 6E can effectively generate a sampling clock to drive the analog-to-digital converters and that real- time radar data can be brought into the SRC 6E via its high speed CHAIN port for performing high speed digital signal processing. / Lieutenant, United States Naval Reserve

Molecular dynamics (MD) is a powerful computer simulation technique providing atomistic resolution across a broad range of time scales. In the past four decades, researchers have harnessed the exponential growth in computer power and applied it to the simulation of diverse molecular systems. Although MD simulations are playing an increasingly important role in biomedical research, sampling limitations imposed by both hardware and software constraints establish a \textit{de facto} upper bound on the size and length of MD trajectories. While simulations are currently approaching the hundred-thousand-atom, millisecond-timescale mark using large-scale computing centres optimized for general-purpose data processing, many interesting research topics are still beyond the reach of practical computational biophysics efforts. The purpose of this work is to design a high-speed MD machine which outperforms standard simulators running on commodity hardware or on large computing clusters. In pursuance of this goal, an MD-specific computer architecture is developed which tightly couples the fast processing power of Field-Programmable Gate Array (FPGA) computer chips with a network of high-performance CPUs. The development of this architecture is a multi-phase approach. Core MD algorithms are first analyzed and deconstructed to identify the computational bottlenecks governing the simulation rate. High-speed, parallel algorithms are subsequently developed to perform the most time-critical components in MD simulations on specialized hardware much faster than is possible with general-purpose processors. Finally, the functionality of the hardware accelerators is expanded into a fully-featured MD simulator through the integration of novel parallel algorithms running on a network of CPUs. The developed architecture enabled the construction of various prototype machines running on a variety of hardware platforms which are explored throughout this thesis. Furthermore, simulation models are developed to predict the rate of acceleration using different architectural configurations and molecular systems. With initial acceleration efforts focused primarily on expensive van der Waals and Coulombic force calculations, an architecture was developed whereby a single machine achieves the performance equivalent of an 88-core InfiniBand-connected network of CPUs. Finally, a methodology to successively identify and accelerate the remaining time-critical aspects of MD simulations is developed. This design leads to an architecture with a projected performance equivalent of nearly 150 CPU-cores, enabling supercomputing performance in a single computer chassis, plugged into a standard wall socket.

Molecular dynamics (MD) is a powerful computer simulation technique providing atomistic resolution across a broad range of time scales. In the past four decades, researchers have harnessed the exponential growth in computer power and applied it to the simulation of diverse molecular systems. Although MD simulations are playing an increasingly important role in biomedical research, sampling limitations imposed by both hardware and software constraints establish a \textit{de facto} upper bound on the size and length of MD trajectories. While simulations are currently approaching the hundred-thousand-atom, millisecond-timescale mark using large-scale computing centres optimized for general-purpose data processing, many interesting research topics are still beyond the reach of practical computational biophysics efforts. The purpose of this work is to design a high-speed MD machine which outperforms standard simulators running on commodity hardware or on large computing clusters. In pursuance of this goal, an MD-specific computer architecture is developed which tightly couples the fast processing power of Field-Programmable Gate Array (FPGA) computer chips with a network of high-performance CPUs. The development of this architecture is a multi-phase approach. Core MD algorithms are first analyzed and deconstructed to identify the computational bottlenecks governing the simulation rate. High-speed, parallel algorithms are subsequently developed to perform the most time-critical components in MD simulations on specialized hardware much faster than is possible with general-purpose processors. Finally, the functionality of the hardware accelerators is expanded into a fully-featured MD simulator through the integration of novel parallel algorithms running on a network of CPUs. The developed architecture enabled the construction of various prototype machines running on a variety of hardware platforms which are explored throughout this thesis. Furthermore, simulation models are developed to predict the rate of acceleration using different architectural configurations and molecular systems. With initial acceleration efforts focused primarily on expensive van der Waals and Coulombic force calculations, an architecture was developed whereby a single machine achieves the performance equivalent of an 88-core InfiniBand-connected network of CPUs. Finally, a methodology to successively identify and accelerate the remaining time-critical aspects of MD simulations is developed. This design leads to an architecture with a projected performance equivalent of nearly 150 CPU-cores, enabling supercomputing performance in a single computer chassis, plugged into a standard wall socket.