Increasing relative semiconductor process variations are making the prediction of
realistic worst-case integrated circuit delay or sign-off yield more difficult. As process
geometries shrink, intra-die variations have become dominant and it is imperative to
model them to obtain accurate timing analysis results. In addition, intra-die process
variations are spatially correlated due to pattern dependencies in the manufacturing
process. Any statistical static timing analysis (SSTA) tool is incomplete without a model
for signal crosstalk, as critical path delays can increase or decrease depending on the
switching of capacitively coupled nets. The coupled signal timing in turn depends on the
process variations. This work describes an SSTA tool that models signal crosstalk and
spatial correlation in intra-die process variations, along with gradients and inter-die
variations.
| Identifer | oai:union.ndltd.org:tamu.edu/oai:repository.tamu.edu:1969.1/2545 |
| Date | 01 November 2005 |
| Creators | Veluswami, Senthilkumar |
| Contributors | Walker, Duncan M. (Hank) |
| Publisher | Texas A&M University |
| Source Sets | Texas A and M University |
| Language | en_US |
| Detected Language | English |
| Type | Book, Thesis, Electronic Thesis, text |
| Format | 332540 bytes, electronic, application/pdf, born digital |
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