Along the history of Very Large Scale Integration (VLSI), we have successfully scaled
down the size of transistors, scaled up the speed of integrated circuits (IC) and the number
of transistors in a chip - these are just a few examples of our achievement in VLSI scaling.
It is projected to enter the nanometer (timing estimation and buffer planning for global routing and other early stages such
as floorplanning. A novel path based buffer insertion scheme is also included, which
can overcome the weakness of the net based approaches. Part-2 Circuit clustering techniques with the application in Field-Programmable
Gate Array (FPGA) technology mapping
The problem of timing driven n-way circuit partitioning with application to FPGA
technology mapping is studied and a hierarchical clustering approach is presented for the latest multi-level FPGA architectures. Moreover, a more general delay model is included in order to accurately characterize the delay behavior of the clusters and circuit elements.
| Identifer | oai:union.ndltd.org:tamu.edu/oai:repository.tamu.edu:1969.1/4922 |
| Date | 25 April 2007 |
| Creators | Sze, Chin Ngai |
| Contributors | Hu, Jiang |
| Publisher | Texas A&M University |
| Source Sets | Texas A and M University |
| Language | en_US |
| Detected Language | English |
| Type | Book, Thesis, Electronic Dissertation, text |
| Format | 956517 bytes, electronic, application/pdf, born digital |
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