The frequency synthesizer, which performs the main role of carrier generation
for the down-conversion/up-conversion operations, is a key building block in radio
transceiver front-ends. The design of a synthesizer for a 2.4 GHz IEEE 802.15.4/Zigbee
transceiver forms the core of this work. This thesis provides a step-by-step procedure for
the design of a frequency synthesizer in a transceiver environment, from the mapping of
standard-specifications to its integrated circuit implementation in a CMOS technology.
The results show that careful system level planning leads to high-performance
realizations of the synthesizer. A strategy of using different supply voltages to enhance
the performance of each building block is discussed. A section is presented on layout and
board level issues, especially for radio-frequency systems, and their effect on synthesizer
performance. The synthesizer consumes 15.5 mW and meets the specifications of the 2.4
GHz IEEE 802.15.4/Zigbee standard. It is capable of 5 GHz operation with a VCO
sensitivity of 135 MHz/V and a tuning range of 700 MHz. It can be seen that the adopted
methodology can be used for the design of high-performance frequency synthesizers for
any narrow-band wireless standard.
| Identifer | oai:union.ndltd.org:tamu.edu/oai:repository.tamu.edu:1969.1/5898 |
| Date | 17 September 2007 |
| Creators | Srinivasan, Rangakrishnan |
| Contributors | Sanchez-Sinencio, Edgar, Silva-Martinez, Jose |
| Publisher | Texas A&M University |
| Source Sets | Texas A and M University |
| Language | en_US |
| Detected Language | English |
| Type | Book, Thesis, Electronic Thesis, text |
| Format | 2823157 bytes, electronic, application/pdf, born digital |
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