Return to search

A Benchmarking Platform For Network-On-Chip (NOC) Multiprocessor System-On- Chips

Network-on-Chip (NOC) based designs have garnered significant attention from both
researchers and industry over the past several years. The analysis of these designs has
focused on broad topics such as NOC component micro-architecture, fault-tolerant
communication, and system memory architecture. Nonetheless, the design of lowlatency,
high-bandwidth, low-power and area-efficient NOC is extremely complex due
to the conflicting nature of these design objectives. Benchmarks are an indispensable
tool in the design process; providing thorough measurement and fair comparison
between designs in order to achieve optimal results (i.e performance, cost, quality of
service).
This research proposes a benchmarking platform called NoCBench for evaluating
the performance of Network-on-chip. Although previous research has proposed standard
guidelines to develop benchmarks for Network-on-Chip, this work moves forward and
proposes a System-C based simulation platform for system-level design exploration. It
will provide an initial set of synthetic benchmarks for on-chip network interconnection
validation along with an initial set of standardized processing cores, NOC components,
and system-wide services.
The benchmarks were constructed using synthetic applications described by Task
Graphs For Free (TGFF) task graphs extracted from the E3S benchmark suite. Two
benchmarks were used for characterization: Consumer and Networking. They are
characterized based on throughput and latency. Case studies show how they can be used
to evaluate metrics beyond throughput and latency (i.e. traffic distribution).
The contribution of this work is two-fold: 1) This study provides a methodology
for benchmark creation and characterization using NoCBench that evaluates important
metrics in NOC design (i.e. end-to-end packet delay, throughput). 2) The developed
full-system simulation platform provides a complete environment for further benchmark
characterization on NOC based MpSoC as well as system-level design space
exploration.

Identiferoai:union.ndltd.org:tamu.edu/oai:repository.tamu.edu:1969.1/ETD-TAMU-2010-12-8662
Date2010 December 1900
CreatorsMalave-Bonet, Javier
ContributorsMahapatra, Rabi N.
Source SetsTexas A and M University
Languageen_US
Detected LanguageEnglish
Typethesis, text
Formatapplication/pdf

Page generated in 0.0019 seconds