As VLSI technology enters the nanoscale regime, a great amount of efforts have
been made to reduce interconnect delay. Among them, buffer insertion stands out
as an effective technique for timing optimization. A dramatic rise in on-chip buffer
density has been witnessed. For example, in two recent IBM ASIC designs, 25% gates
are buffers.
In this thesis, three buffer insertion algorithms are presented for the procedure
of performance and power optimization. The second chapter focuses on improving circuit performance under inductance effect. The new algorithm works under
the dynamic programming framework and runs in provably linear time for multiple
buffer types due to two novel techniques: restrictive cost bucketing and efficient delay
update. The experimental results demonstrate that our linear time algorithm consistently outperforms all known RLC buffering algorithms in terms of both solution
quality and runtime. That is, the new algorithm uses fewer buffers, runs in shorter
time and the buffered tree has better timing.
The third chapter presents a method to guarantee a high fidelity signal transmission in global bus. It proposes a new redundant via insertion technique to reduce
via variation and signal distortion in twisted differential line. In addition, a new
buffer insertion technique is proposed to synchronize the transmitted signals, thus
further improving the effectiveness of the twisted differential line. Experimental results demonstrate a 6GHz signal can be transmitted with high fidelity using the new
approaches. In contrast, only a 100MHz signal can be reliably transmitted using a
single-end bus with power/ground shielding. Compared to conventional twisted differential line structure, our new techniques can reduce the magnitude of noise by 45%
as witnessed in our simulation.
The fourth chapter proposes a buffer insertion and gate sizing algorithm for
million plus gates. The algorithm takes a combinational circuit as input instead of
individual nets and greatly reduces the buffer and gate cost of the entire circuit.
The algorithm has two main features: 1) A circuit partition technique based on the
criticality of the primary inputs, which provides the scalability for the algorithm, and
2) A linear programming formulation of non-linear delay versus cost tradeoff, which
formulates the simultaneous buffer insertion and gate sizing into linear programming
problem. Experimental results on ISCAS85 circuits show that even without the circuit
partition technique, the new algorithm achieves 17X speedup compared with path
based algorithm. In the meantime, the new algorithm saves 16.0% buffer cost, 4.9%
gate cost, 5.8% total cost and results in less circuit delay.
| Identifer | oai:union.ndltd.org:tamu.edu/oai:repository.tamu.edu:1969.1/ETD-TAMU-2024 |
| Date | 15 May 2009 |
| Creators | Jiang, Zhanyuan |
| Contributors | Shi, Weiping |
| Source Sets | Texas A and M University |
| Language | en_US |
| Detected Language | English |
| Type | thesis, text |
| Format | electronic, application/pdf, born digital |
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