Moore’s Law has driven a continuous demand for decreasing feature sizes used
in Very Large Scale Integrated (VLSI) technology which has outpaced the solutions
offered by lithography hardware. Currently, a light wavelength of 193nm is being used
to print sub-65nm features. This introduces process variations which cause mismatches
between desired and actual wafer feature sizes. However, the layout which affects the
printability of a circuit can be modified in a manner which can make it more
lithography-friendly.
In this work, we intend to implement these modifications as a series of
perturbations on the initial layout generated by the CAD tool for the circuit. To
implement these changes we first calculate the feature variations offline on the
boundaries of all possible standard cell pairs used in the circuit layout and record them in
a Look-Up Table (LUT). After the CAD tool generates the initial placement of the
circuit, we use the LUT to estimate the variations on the boundaries of all the standard
cells. Depending on the features which may have the highest feature variations we assign
a cost to the layout and our aim is now to reduce the cost of the layout after
implementing perturbations which could be a simple cell flip or swap with a neighboring
cell. The algorithm used to generate a circuit placement with a low cost is Simulated
Annealing which allows a high probability for a solution with a higher cost to be
selected during the initial iterations and as time goes on it tends closer to the greedy
algorithm. The idea here is to avoid a locally optimum solution. It is also essential to minimize the impact of the iterations performed on the initial solution in terms of
wirelength, vias and routing congestion.
We validate our procedure on ISCAS85 benchmark circuits by simulating dose
and defocus variations using the Mentor tool Calibre LFD. We obtain a reduction of
greater 20% in the number of instances with the highest cell boundary feature variations.
The wirelength and the number of vias showed an increase of roughly 2.2-8.8% and 1.2-
7.8% respectively for different circuits. The routing congestion by and large remains
unaffected.
| Identifer | oai:union.ndltd.org:tamu.edu/oai:repository.tamu.edu:1969.1/ETD-TAMU-3120 |
| Date | 15 May 2009 |
| Creators | Shah, Pratik Jitendra |
| Contributors | Hu, Jiang |
| Source Sets | Texas A and M University |
| Language | en_US |
| Detected Language | English |
| Type | Book, Thesis, Electronic Thesis, text |
| Format | electronic, application/pdf, born digital |
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