Thesis (MArch(Prof) (Architecture))--University of Pretoria, 2008.

Thesis (M.Arch.)--University of Detroit Mercy, 2008.

This degree work aims to tell a story about the force of fashion. Through forced material interactions on body the focus of this study is interaction. Interaction between contrasting materials, body and space and/or catwalk and audience. By forcing materials to act and interact on body this work aims to nd new expressions and ways of making in fashion. To tell this story a design space was made, ‘Wonderland’, a place where all the ‘Wonder Women’ live. These ‘Wonder Women' are like sisters, di erent from the other. The resemblance lies in the interaction and forceful expression. This collection is the result of a thorough material investigation resulting in a lineup of seven looks. Each made in di erent techniques, the possibilities within this study are endless. This work proposes to all within the fashion eld to not be afraid, to step away from the season-hysteria and do what you want. Tell that story, and may the force be with you.

Thesis (Ph. D.)--College of Architecture, Georgia Institute of Technology, 2004. Directed by Craig M. Zimring. / Includes bibliographical references (leaves 243-257).

Thesis (M. Arch.)--University of Hong Kong, 2004. / Includes special report study entitled: Virtual spaces reality and its effects on the physical. Also available in print.

The practice of queuing is a daily experience for most of us and it is usually difficult to combine it with other activities. This indicates that people involved in the act of queuing become a bit too occupied with maintaining one's position in the queue. Despite that queuing is a common phenomenon, queuing situations are now often equipped with aids based on numbers that help regulating the queuing order. Still, the practice of queuing includes several nuances of social interaction that demands careful attention from its participants for it to work. Based on cases and concepts with varying levels of viability, this thesis investigates the practice of queuing as a design space. The thesis further suggests how a more flexible queue could be designed. An overall aim is to examine how to provide greater action space for participants in a queue and enable for new forms of interaction. In order to queue from a distance, much of what traditionally constructs the queue is redesigned. To address these issues from a usability point of view, it is a challenge to create an interaction design that allows different ways of queuing, without deviating too much from features that are evaluated as decisive to maintain.

The automatic generation of instruction set extensions to provide application-specific acceleration for embedded processors has been a productive area of research in recent years. There have been incremental improvements in the quality of the algorithms that discover and select which instructions to add to a processor. The use of automatic algorithms, however, result in instructions which are radically different from those found in conventional, human-designed, RISC or CISC ISAs. This has resulted in a gap between the hardware’s capabilities and the compiler’s ability to exploit them. This thesis proposes and investigates the use of a high-level compiler pass that uses graph-subgraph isomorphism checking to exploit these complex instructions. Operating in a separate pass permits techniques to be applied that are uniquely suited for mapping complex instructions, but unsuitable for conventional instruction selection. The existing, mature, compiler back-end can then handle the remainder of the compilation. With this method, the high-level pass was able to use 1965 different automatically produced instructions to obtain an initial average speed-up of 1.11x over 179 benchmarks evaluated on a hardware-verified cycle-accurate simulator. This result was improved following an investigation of how the produced instructions were being used by the compiler. It was established that the models the automatic tools were using to develop instructions did not take account of how well the compiler could realistically use them. Adding additional parameters to the search heuristic to account for compiler issues increased the speed-up from 1.11x to 1.24x. An alternative approach using a re-designed hardware interface was also investigated and this achieved a speed-up of 1.26x while reducing hardware and compiler complexity. A complementary, high-level, method of exploiting dual memory banks was created to increase memory bandwidth to accommodate the increased data-processing bandwidth provided by extension instructions. Finally, the compiler was considered for use in a non-conventional role where rather than generating code it is used to apply source-level transformations prior to the generation of extension instructions and thus affect the shape of the instructions that are generated.

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No description available.

Advanced Encryption Standard is new standard for data encryption and decryption.There is a lot of relevant research so far, but how to find out the suitable design according to the demand has become an important question. So we consult different improvement methods from relevant research, do the design space exploration of AES hardware circuit design with the modeling of parameterized IP Generator.We choose non-feedback mode AES design, which can offer higher security. Using the submodule as different design parameter such as SubBytes/InvSubBytes¡BMixColumns/InvMixColumns¡BKeyExpansion to form many kinds of AES hardware circuit. SubBytes/InvSubBytes¡BMixColumns/InvMixColumns module include two different structure, Integrated and Separate Encryption/Decryption module. KeyExpansion module include two different structure, on the fly and Store in Rom.There are three different keylength 128¡B192¡B256, which can form forteen different structure. We provide circuit gate count¡Bthroughput¡Bpower consumption information of different AES hardware citcuit design by the synthesis and gate-level simulation result. According to our implementation, the user can choose the suitable AES hardware circuit design method and which can solve the problem above. We also provide an automatic test pattern generator for our design verification, it makes our design can be integrated efficiently. Our experiment result show that, the design which Encryption/Decryption module use integrated structure have less circuit gate count than which Encryption/Decryption module use separate structure while throughput constraint is between 700MHz to 1300MHz (It¡¦s depend on different keylength combination). But while the throughput constraint become higher, the circuit gate count of integrated structure rise faster than separate structure. And the situation is the same with power consumption.The maximum throughput of KeyExpansion module use store in Rom structure is higher than whcich use on the fly structure.