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OFDM (Orthogonal Frequency Division Multiplexing) technology, due to its longer symbol duration that decease the amount of dispersion in time caused by multipath delay spread, has been widely used in many advanced digital communication systems such as DVB (Digital Video Broadcast), WLAN (Wireless Local Area Network), and UWB (Ultra Wide Band). How to realize efficient OFDM systems has been a very important issue for either academic or industry fields in recent years. This thesis aims to explore the VLSI implementation of the OFDM system targeted on its application on the wildly popular IEEE802.11a WLAN systems. An efficient OFDM architecture design involves the algorithm exploration and the tradeoff between the algorithm performance and hardware implementation. Therefore, in this thesis, a Matlab simulation platform for the IEEE802.11a baseband receiver is first built to refine several key synchronization algorithms including frame detection, timing recovery, carrier frequency offset, channel estimation as well as phase tracking under some given channel models. An excellent frame detection and timing recovery method is adopted such that nearly perfect synchronization can be achieved at SNR> 3. Furthermore, area-efficient architecture suitable for VLSI implementation for each synchronization module has also been proposed. In summary, 4 complex multipliers with 388 shift registers are required in our synchronization circuits. These modules are integrated with a core single-path radix-23 IFFT (Inverse Fast Fourier Transform) block to build a highly efficient WLAN baseband.

¡@¡@A single chip of variable length FFT processor is presented in this thesis. This processor can be applied for the applications with 128/256/512/1024/2048-point FFT. This processor is based on SDF (single path delay feedback) pipeline architecture with radix-2^3 computation element. The number of bits for input data and twiddle factors is carefully selected by system simulation to meet the requirements of OFDM system. In addition, we propose a feedback twiddle factor generator to instead the lookup table for twiddle factors to reduce the storage size of memory. The FFT processor is carried out by CMOS 0.35£gm 2P4M process with core area 3.381x3.3625 mm^2. In the gate level simulation, the output data rate of this FFT processor is above 22.72MHz, so the processor can meet the requirement of IEEE 802.16e standard.

Thesis (M.S.)--Ohio State University, 2009. / Title from first page of PDF file. Includes vita. Includes bibliographical references (p. 51-54).

Thesis (Ph. D.)--School of Electrical and Computer Engineering, Georgia Institute of Technology, 2004. Directed by Monson H. Hayes. / Vita. Includes bibliographical references (leaves 134-139).

Thesis (Ph. D.)--Electrical and Computer Engineering, Georgia Institute of Technology, 2004. / John A. Buck, Committee Chair ; Stephen E. Ralph, Committee Member ; Gee-Kung Chang, Committee Member ; Rick Trebino, Committee Member ; Glenn S. Smith, Committee Member. Includes bibliographical references (leaves 102-104).

Thesis (M. Phil.)--University of Hong Kong, 1989.

published_or_final_version / Mechanical Engineering / Master / Master of Philosophy

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