An integral part of neuropsychological assessment is the measurement of sensory-motor performance. Many studies have been conducted on the effectiveness of neuropsychological batteries to assess neurological impairment, however examination of only the sensory-motor portion of those measures has been limited. Investigations of tests of sensory and motor functions have often limited their analysis to single tests. The present study assessed the ability of the Dean-Woodcock Sensory Motor Battery (DWSMB), part of a new neuropsychological measure, the Dean-Woodcock Neuropsychological Battery (DWNB), to distinguish between normal subjects and neurologically impaired individuals as diagnosed by a neurologist. Scores from the subtests of the DWSMB from an existing data set for 250 normal and 250 neurologically impaired individuals were randomly assigned to two equal groups to allow for cross validation. Results indicated that the DWSMB was able to correctly identify 92.8% of the cases, identifying 94.4% of the normal population and 91.2% of the neurologically impaired subjects. An additional discriminant analysis was conducted to establish the accuracy of the DWSMB to identify individual diagnoses within neurologically impaired and normal subjects. The DWSMB correctly identified the following cases: 44.9% cardio-vascular accidents, 66.7% multiple sclerosis, 40% seizures, 42% traumatic brain injuries, 62.7% dementia, and 54.5% Parkinson's disease. Results indicated the usefulness of the DWSMB in identifying neurological damage and specific diagnoses in a relatively quick assessment. The utility of the DWSMB and the use of standardized administration procedures, behavioral information for evaluation, and measures of subcortical functions was discussed in light of future research. The potential use of the DWSMB in clinical and educational settings was also considered. / Department of Educational Psychology

The ever-increasing design complexity of modern circuits challenges our ability to verify their correctness. Therefore, various errors are more likely to escape the pre-silicon verification process and to manifest themselves after design tape-out. To address this problem, effective post-silicon validation is essential for eliminating design bugs before integrated circuit (IC) products shipped to customers. In the debug process, it becomes increasingly popular to insert design-for-debug (DfD) structures into the original design to facilitate real-time debug without intervening the circuits’ normal operation. For this so-called trace-based post-silicon validation technique, the key question is how to design such DfD circuits to achieve sufficient observability and controllability during the debug process with limited hardware overhead. However, in today’s VLSI design flow, this is unfortunately conducted in a manual fashion based on designers’ own experience, which cannot guarantee debug quality. To tackle this problem, we propose a set of automatic tracing solutions as well as innovative DfD designs in this thesis. First, we develop a novel trace signal selection technique to maximize the visibility on debugging functional design errors. To strengthen the capability for tackling these errors, we sequentially introduce a multiplexed signal tracing strategy with a trace signal grouping algorithm for maximizing the probability of catching the propagated evidences from functional design errors. Then, to effectively localize speedpathrelated electrical errors, we propose an innovative trace signal selection solution as well as a trace qualification technique. On the other hand, we introduce several low-cost interconnection fabrics to effectively transfer trace data in post-silicon validation. We first propose to reuse the existing test channel for real-time trace data transfer, so that the routing cost of debug hardware is dramatically reduced. The method is further improved to avoid data corruption in multi-core debug. We then develop a novel interconnection fabric design and optimization technique, by combining multiplexor network and non-blocking network, to achieve high debug flexibility with minimized hardware cost. Moreover, we introduce a hybrid trace interconnection fabric that is able to tolerate unknown values in “golden vectors“, at the cost of little extra DfD overhead. With the fabric, we develop a systematic signal tracing procedure to automatically localize erroneous signals with just a few debug runs. Our empirical evaluation shows that the solutions presented in this thesis can greatly improve the validation quality of VLSI circuits, and ultimately enable the design and fabrication of reliable electronic devices. / Liu, Xiao. / Thesis (Ph.D.)--Chinese University of Hong Kong, 2012. / Includes bibliographical references (leaves 143-152). / Electronic reproduction. Hong Kong : Chinese University of Hong Kong, [2012] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Abstract --- p.i / Acknowledgement --- p.iv / Preface --- p.vii / Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- VLSI Design Trends and Validation Challenges --- p.1 / Chapter 1.2 --- Key Contributions and Thesis Outline --- p.4 / Chapter 2 --- State of the Art on Post-Silicon Validation --- p.8 / Chapter 2.1 --- Trace Signal Selection --- p.12 / Chapter 2.2 --- Interconnection Fabric Design for Trace Data Transfer --- p.14 / Chapter 2.3 --- Trace Data Compression --- p.15 / Chapter 2.4 --- Trace-Based Debug Control --- p.16 / Chapter 3 --- Signal Selection for Visibility Enhancement --- p.18 / Chapter 3.1 --- Preliminaries and Summary of Contributions --- p.19 / Chapter 3.2 --- Restorability Formulation --- p.23 / Chapter 3.2.1 --- Terminologies --- p.23 / Chapter 3.2.2 --- Gate-Level Restorabilities --- p.24 / Chapter 3.3 --- Trace Signal Selection --- p.28 / Chapter 3.3.1 --- Circuit Level Visibility Calculation --- p.28 / Chapter 3.3.2 --- Trace Signal Selection Methodology --- p.30 / Chapter 3.3.3 --- Trace Signal Selection Enhancements --- p.31 / Chapter 3.4 --- Experimental Results --- p.34 / Chapter 3.4.1 --- Experiment Setup --- p.34 / Chapter 3.4.2 --- Experimental Results --- p.35 / Chapter 3.5 --- Conclusion --- p.40 / Chapter 4 --- Multiplexed Tracing for Design Error --- p.47 / Chapter 4.1 --- Preliminaries and Summary of Contributions --- p.49 / Chapter 4.2 --- Design Error Visibility Metric --- p.53 / Chapter 4.3 --- Proposed Methodology --- p.56 / Chapter 4.3.1 --- Supporting DfD Hardware for Multiplexed Signal Tracing --- p.58 / Chapter 4.3.2 --- Signal Grouping Algorithm --- p.58 / Chapter 4.4 --- Experimental Results --- p.62 / Chapter 4.4.1 --- Experiment Setup --- p.62 / Chapter 4.4.2 --- Experimental Results --- p.63 / Chapter 4.5 --- Conclusion --- p.66 / Chapter 5 --- Tracing for Electrical Error --- p.68 / Chapter 5.1 --- Preliminaries and Summary of Contributions --- p.69 / Chapter 5.2 --- Observing Speedpath-Related Electrical Errors --- p.71 / Chapter 5.2.1 --- Speedpath-Related Electrical Error Model --- p.71 / Chapter 5.2.2 --- Speedpath-Related Electrical Error Detection Quality --- p.73 / Chapter 5.3 --- Trace Signal Selection --- p.75 / Chapter 5.3.1 --- Relation Cube Extraction --- p.76 / Chapter 5.3.2 --- Signal Selection for Non-Zero-Probability Error Detection --- p.77 / Chapter 5.3.3 --- Trace Signal Selection for Error Detection Quality Enhancement --- p.78 / Chapter 5.4 --- Trace Data Qualification --- p.80 / Chapter 5.5 --- Experimental Results --- p.83 / Chapter 5.6 --- Conclusion --- p.87 / Chapter 6 --- Reusing Test Access Mechanisms --- p.88 / Chapter 6.1 --- Preliminaries and Summary of Contributions --- p.89 / Chapter 6.1.1 --- SoC Test Architectures --- p.89 / Chapter 6.1.2 --- SoC Post-Silicon Validation Architectures --- p.90 / Chapter 6.1.3 --- Summary of Contributions --- p.92 / Chapter 6.2 --- Overview of the Proposed Debug Data Transfer Framework --- p.93 / Chapter 6.3 --- Proposed DfD Structures --- p.94 / Chapter 6.3.1 --- Modified Wrapper Design --- p.95 / Chapter 6.3.2 --- Trace Buffer Interface Design --- p.97 / Chapter 6.4 --- Sharing TAM for Multi-Core Debug Data Transfer --- p.98 / Chapter 6.4.1 --- Core Masking for TestRail Architecture --- p.98 / Chapter 6.4.2 --- Channel Split --- p.99 / Chapter 6.5 --- Experimental Results --- p.101 / Chapter 6.6 --- Conclusion --- p.104 / Chapter 7 --- Interconnection Fabric for Flexible Tracing --- p.105 / Chapter 7.1 --- Preliminaries and Summary of Contributions --- p.106 / Chapter 7.2 --- Proposed Interconnection Fabric Design --- p.111 / Chapter 7.2.1 --- Multiplexer Network for Mutually-Exclusive Signals --- p.111 / Chapter 7.2.2 --- Non-Blocking Concentration Network for Concurrently-Accessible Signals --- p.114 / Chapter 7.3 --- Experimental Results --- p.117 / Chapter 7.4 --- Conclusion --- p.121 / Chapter 8 --- Interconnection Fabric for Systematic Tracing --- p.123 / Chapter 8.1 --- Preliminaries and Summary of Contributions --- p.124 / Chapter 8.2 --- Proposed Trace Interconnection Fabric --- p.128 / Chapter 8.3 --- Proposed Error Evidence Localization Methodology --- p.130 / Chapter 8.4 --- Experimental Results --- p.133 / Chapter 8.4.1 --- Experimental Setup --- p.133 / Chapter 8.4.2 --- Results and Discussion --- p.134 / Chapter 8.5 --- Conclusion --- p.139 / Chapter 9 --- Conclusion --- p.140 / Bibliography --- p.152

This dissertation describes an innovative approach to the state justification portion of the sequential circuit automatic test pattern generation (ATPG) process. Given the absence of a stored fault an ATPG controller invokes some combinational circuit test generation procedure, such as the D-algorithm, to identify a circuit state (goal state) and input vectors that will sensitize a selected fault. The state justification phase then finds a transfer sequence to the goal from the present state. A forward fault propogation search can be successfully guided through state space from the present state but the forward justification search is less efficient and the failure rate is high. The backward function level search invokes inverse RTL level primitives and exploits easy movement of data vectors in structured VLSI circuits. Examples illustrated are in AHPL. This search is equally applicable to an RTL level subset of VHDL. Combinational logic units are treated as functions and the circuit states are partitioned into control states and data states. The search proceeds backwards over the control state space starting from the goal state node and data states are transformed according to the control flow. Vectorized data paths in VLSI circuits and search guiding heuristics which favor convenient inverse functions keep the number of search nodes low. Partial covers, conceptually similar to singular covers in D-algorithm, model the inverse functions of combinational logic units. The search successfully terminates when a child state node logically matches the present state and the present state values can satisfy all the constraints encountered along the search path.

by Chan Lap-kong. / Thesis (M.Phil.)--Chinese University of Hong Kong, 1994. / Includes bibliographical references (leaves 77-80). / ABSTRACT / ACKNOWLEDGEMENTS / LIST OF FIGURES / Chapter 1. --- INTRODUCTION --- p.1 / Chapter 1.1 --- Background --- p.1 / Chapter 1.2 --- Problems in Testing VLSI Circuits --- p.3 / Chapter 1.2.1 --- Test-cost-per-gate --- p.3 / Chapter 1.2.2 --- Tester Complexity --- p.3 / Chapter 1.3 --- Tester Based on Terminals Characteristics -Automatic Testing Equipment(ATE) --- p.4 / Chapter 1.4 --- Tester Based on Terminal and Internal Characteristics --- p.6 / Chapter 1.4.1 --- Mechanical Probing Method --- p.6 / Chapter 1.4.2 --- E-beam Probing Method --- p.7 / Chapter 1.5 --- Movitation for this Research --- p.7 / Chapter 1.6 --- Outline of the Remaining Chapters --- p.9 / Chapter 2. --- E-BEAM TESTER --- p.10 / Chapter 2.1 --- State-of-art of E-Beam Tester --- p.10 / Chapter 2.2 --- An Electron-optical Column of a SEM --- p.12 / Chapter 2.3 --- Beam Rastering Methods --- p.13 / Chapter 2.4 --- Voltage Contrast Phenomenon --- p.14 / Chapter 2.5 --- Configuration of an E-Beam Test System --- p.18 / Chapter 2.6 --- Advantages of an E-beam Tester --- p.20 / Chapter 3. --- BASIC PRINCIPLES --- p.21 / Chapter 3.1 --- Single-Stuck-At Fault Model --- p.21 / Chapter 3.2 --- Observability and Controllability --- p.24 / Chapter 3.3 --- Netlist Format --- p.25 / Chapter 3.4 --- Level --- p.27 / Chapter 3.5 --- Reconvergent Fanout --- p.28 / Chapter 4. --- CONVENTIONAL TEST GENERATION --- p.29 / Chapter 4.1 --- Conventional Automatic Test Generation for ATEs --- p.29 / Chapter 4.3 --- Conventional E-Beam Test Generation --- p.31 / Chapter 5. --- TEST AND PROBE POINT GENERATION --- p.32 / Chapter 5.1 --- Wafer Stage E-beam Testing --- p.32 / Chapter 5.2 --- Critical Paths Generation --- p.33 / Chapter 5.3 --- Assumptions of the Test and Probe Point Generation Algorithm --- p.35 / Chapter 5.4 --- Rules of the Test and Probe Point Generation Algorithm --- p.36 / Chapter 5.5 --- Probe Points Selection and Reduction --- p.38 / Chapter 5.6 --- Test and Probe Point Generation Algorithm --- p.40 / Chapter 5.7 --- Propagation and Justification at Fanout Site --- p.42 / Chapter 6. --- EXAMPLES --- p.45 / Chapter 6.1 --- Example of Test and Probe Point Generation for Circuit sc2 --- p.45 / Chapter 6.2 --- Example of Test and Probe Point Generation for Circuit sfc4 --- p.53 / Chapter 7. --- CONCLUSIONS --- p.61 / Chapter 7.1 --- Summary of Results --- p.61 / Chapter 7.2 --- Further Research --- p.63 / APPENDIX / Appendix A: Algorithm to Find Reconvergent Fanouts / Appendix B: Results of Test Generation for Circuit sc1 / Appendix C: Results of Test Generation for Circuit sc3 / REFERENCES --- p.77

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The main purpose of the present study was to identify sensory-motor deficits caused by closed head injury (CHI) when individuals with CHI are compared to a normal sample. The study also investigated lower-level sensory-motor functioning, such as gait, balance, and coordination and its relation to neurological impairment related to CHI. Additionally, the study determined if age significantly influenced sensory-motor functioning.Archival data was utilized to complete the study. Data was collected from a large, Midwestern neurology clinic (CHI) as well as from a normative sample of individuals with no reported history of neurological impairment. Preliminary analyses were completed to identify outliers. Samples were then randomly selected from the impaired group (CHI) and matched with randomly selected subjects from the normative sample based upon age.Three separate analyses were completed. The first analysis focused on age and if age significantly influences sensory motor functioning. The second analysis was completed using an adult's only sample based upon the results that age significantly influenced sensory-motor performance. Finally, the third analysis utilized all age groups to determine how dramatically age had an impact on distinguishing between individuals with CHI versus a normative sample.Results demonstrated that age had a significant influence on sensory-motor performance. Measures of subcortical and cortical motor function, motor speed, motor coordination and tactile examination were able to accurately classify individuals with head injury from a normative sample to a clinically significant degree (78%). The study argues that the D-WSMB is a reliable and valid measure to utilize when evaluating individuals with CHI. / Department of Educational Psychology

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