Reed-Solomon (RS) codes are non-binary, forward error-correcting codes. The RS code is flexible, in that a code can be shortened, extended, interleaved and concatenated. This flexibility has made the RS code an important design block in communication system design and today the RS code is used within a large number of applications from data storage systems to space telecommunications. Implementations of the coding and decoding strategies have until recently been limited to software due to their high complexity, however, with recent advances in IC fabrication technology it has become possible for RS codecs to be implemented in hardware. A hardware implementation has a smaller silicon requirement, and makes the technology a more applicable solution for real-time applications. However, the problem for a hardware RS codec design solution today is the acknowledged lack of codec design experts. The work outlined in this document addresses this problem through the use of Design Automation (DA). This thesis describes a solution that employs a non-proprietary, technology independent generic VHDL core. The core is a single, self-contained generic circuit description, written entirely in standard synthesizable VHDL and can therefore be used by any synthesis tool on any CAD system to produce a gate-level description for any available technology. The core developed implements a bit-serial RS codec, using a time domain algorithm for encoding, and a frequency domain algorithm for decoding. Only a limited number of code description parameters are required to be entered into the core to produce a completed design in seconds. The results presented in the thesis illustrate in detail that the VHDL core generates efficient circuit architecture in terms of silicon area which are within I% of hand-crafted designs. Comparison of synthesized results to hand crafted designs are presented for all circuit structures from the simplest multiplier up to entire encoders and decoders. Technology independence has been illustrated through the use of synthesis of the core to a traditional semi-custom gate array, LSI Logic LCA300k series, and to a popular Xilinx FPGA. The actual circuit topology, and therefore the route of the circuit critical paths, for the gate array implementation are almost identical to the handcrafted design., since the VHDL core was based on experience gained in creating those circuits. The only differences are attributable to minor differences in synthesis cell libraries that affect the circuit topology in a small way and of course the resulting maximum clock rate which wi11 always be technology-dependent. Obviously, for other architectures, for example FPGAs, the actual route of the critical paths will also be different, but the technology dependence of the critical path is beyond the scope of this thesis.

在如同全IP網路(ALL-IP Network)這類的分封交換網路(packet-switching network)中提供具時效性的服務(time-sensitive services)必須嚴格的控制時間。路由規劃是網路管理中重要的一環，所以這類網路的路由規劃必須考慮網路延遲。然而就我們目前所知，多數的傳統路由演算法並不以傳輸延遲(path delay)為主要考量因素；例外少數有考量延遲時間的演算法也僅限於鍊結延遲(link delay)，而未考慮節點延遲(node delay)。此乃肇因於以往頻寬的成本極為昂貴，因而造成演算法設計者在設計時會儘可能有效利用頻寬，如此免不了會犧牲傳遞速度。在過去幾年間，由於光通訊技術的提升，網路頻寬的成長速度遠遠已超過路由器(router)處理能力的成長。在這樣不對等的成長比例驅使下，節點延遲，亦即路由器處理封包時所耗時間，在傳輸延遲中所佔的比例亦隨之快速增長。也因此我們認為，在為高速封包交換網路設計路由演算法時，必須同時考量鍊結延遲和節點延遲。在本論文中，我們設計了一個訊務流為基礎的路由演算法(flow-based routing algorithm)，KLONE，來驗證我們的論點。在規劃路由時，KLONE會把發生在鍊結和節點上的延遲時間一併列入計算，並以全體延遲時間為主要考量。透過我們反覆的測試實驗，我們發現其較之於常用的OSPF演算法，可以在效能上有30%的勝出。藉此，我們的論點得到初步的證實。 / Providing time sensitive services becomes an essential task for some packet-switching networks such as All-IP networks, which will carry all the traffics supported by both circuit-switching and packet-switching networks. To fulfill this demand, such networks require a delay sensitive routing mechanism to provide time-related QoS for delay sensitive services. However, most of traditional routing algorithms do not take delay time as a major concern. Only a few are designed for time sensitive services. These time sensitive routing algorithms are designed at the time when the link bandwidth is the only scarce resource. As the bandwidth of communication links grows rapidly in recent years due to the advance of optical communication technologies, link bandwidth is no longer the only scarce resource. The processing speed of nodes, for example, routers, becomes another critical source of delay time. In this thesis, we designed a new flow-based routing algorithm, the KLONE algorithm, which takes average delay time as its minimization objective and takes both nodes and links as delay components. Through an intensive evaluation using simulation method, we demonstrate that a routing algorithm that considers both link and node delay might outperform the traditional OSPF algorithm.

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