FPGA clock frequencies are slow enough that only a fraction of the interconnect’s bandwidth is used. By exploiting this bandwidth, the transfer of large amounts of data can be greatly accelerated. Alternatively, it may also be possible to save area on fixed-bandwidth links by using on-chip serial signaling. For datapath-intensive designs which operate on words instead of bits, this can reduce wiring congestion as well. This thesis proposes relatively simple circuit-level modifications to FPGA interconnect to enable high-bandwidth communication. High-level area estimates indicate a potential interconnect area savings of 10 to 60% when serial links are used. Two interconnect pipelining techniques, wave pipelining and surfing, are adapted to FPGAs and compared against each other and against regular FPGA interconnect in terms of throughput, reliability, area, power, and latency. Source-synchronous signaling is used to achieve high data rates with simple receiver design. Statistical models for high-frequency power supply noise are developed and used to estimate the probability of error of wave pipelined and surfing links as a function of link length and operating speed. Surfing is generally found to be more reliable and less sensitive to noise than wave pipelining. Simulation results in a 65nm process demonstrate a throughput of 3Gbps per wire across a 50-stage, 25mm link. / Applied Science, Faculty of / Electrical and Computer Engineering, Department of / Graduate

The transient time-domain simulation, of the circuit response, is a fundamental component in the Computer-Aided Design tools of all integrated circuit and systems. It is typically desirable that a method adopted in the transient circuit simulator be of high- order and numerically stable. The two requirements, however, proved to be in conflict with each other, especially in the larger class of methods that were used in traditional circuit simulators. Recent work based on utilizing the Obreshkov formula has proved that it is possible to combine the high order with the numerical stability. The objective of this thesis is to show how the present implementation of the Obreshkov- based method can be improved and generalized to handle different types of circuits. The first aspect of improvement targets the computation of the high-order derivatives re- quired by the Obreshkov formula. The second aspect of improvement, presented in the thesis, develops a generalized formulation that takes into account the presence of non- linear memory elements, whose nonlinearity is based on a capacitive or inductive-based nonlinear model.

This thesis describes a new approach to accelerate the simulation of the steady-state response of nonlinear circuits using the Harmonic Balance (HB) technique. The approach presented in this work focuses on direct factorization of the sparse Jacobian matrix of the HB nonlinear equations using a Graphics Processing Unit (GPU) platform. This approach exploits the heterogeneous structure of the Jacobian matrix. The computational core of the proposed approach is based on developing a block-wise version of the KLU factorization algorithm, where scalar arithmetic operations are replaced by block-aware matrix operations. For a large number of harmonics, or excitation tones, or both the Block-KLU (BKLU) approach effectively raises the ratio of floating-point operations to other operations and, therefore, becomes an ideal vehicle for implementation on a GPU-based platform. Motivated by this fact, a GPU-based Hybrid Block KLU framework is developed to implement the BKLU. The proposed approach in this thesis is named Hybrid-BKLU. The Hybrid-BKLU is implemented in two parts, on the host CPU and on the graphic card’s GPU, using the OpenCL heterogeneous parallel programming language. To show the efficiency of the Hybrid-BKLU approach, its performance is compared with BKLU approach performing HB analysis on several test circuits. The Hybrid-BKLU approach yields speedup by up to 89 times over conventional BKLU on CPU.

Hall Effect integrated circuits are used in a wide range of applications to measure the strength and/or direction of magnetic fields. These sensors play an increasingly significant role in the fields of automation, medical treatment and detection thanks largely to the enormous development of information technologies and electronic industries. Commercial Hall Effect ICs available in the market are all based on silicon technology. These ICs have the advantages of low cost and compatibility with CMOS technology, but suffer from poor sensitivity and detectability, high power consumption and low operating frequency bandwidths. The objective of this work was to develop and fabricate the first fully monolithic GaAs-InGaAs-AlGaAs 2-Dimensional Electron Gas (2DEG) Hall Effect integrated circuits whose performance enhances pre-existing technologies. To fulfil this objective, initially 2 µm gate length pHEMTs and 60/20 µm (L/W) Greek cross Hall Effect sensors were fabricated on optimised GaAs-In.18Ga.82As-Al.35Ga.65As 2DEG structures (XMBE303) suitable for both sensor and integrated circuit designs. The pseudomorphic high electron mobility transistors (pHEMTs) produced state-of-the-art output conductance, providing high intrinsic gain of 405, current cut-off frequency of 4.8 GHz and a low negative threshold voltage of -0.4 V which assisted in designing single supply ICs with high sensitivity and wide dynamic range. These pHEMTs were then accurately modelled for use in the design and simulation of integrated circuits. The corresponding Hall sensor showed a current sensitivity of 0.4 mV/mA.mT and a maximum magnetic DC offset of 0.35 mT at 1 V. DC digital (unipolar) and DC linear Hall Effect integrated circuits were then designed, simulated, fabricated and fully characterised. The DC linear Hall Effect IC provided an overall sensitivity of 8 mV/mT and a power consumption as low as 6.35 mW which, in comparison with commercial Si DC linear Hall ICs, is at least a factor of 2 more power efficient. The DC digital (unipolar) Hall Effect IC demonstrated a switching sensitivity of 6 mT which was at least ~50% more sensitive compared to existing commercial unipolar Si Hall ICs. In addition, a novel low-power GaAs-InGaAs-AlGaAs 2DEG AC linear Hall Effect integrated circuit with unprecedented sensitivity and wide dynamic range was designed, simulated, fabricated and characterised. This IC provided a sensitivity of 533 nV/nT, minimum field detectability of 177 nT (in a 10 Hz bandwidth) at frequencies from 500 Hz up to 200 kHz, consuming only 10.4 mW of power from a single 5 V of supply. In comparison to commercial Si linear Hall ICs, this IC provides an order of magnitude larger sensitivity, a factor of 4 higher detectability, 20 times wider bandwidth and over 20% lower power consumption (10.4 mW vs. 12.5 mW). These represent the first reported monolithic integrated circuits using a CMOS-like technology but in GaAs 2DEG technology and are extremely promising as complements, if not alternatives, to CMOS Si devices in high performance applications (such as high temperatures operations (>150 °C) and radiation hardened environment in the nuclear industry).

Testing an integrated circuit once it has been manufactured is required in order to identify faulty and fault-free circuits. As the complexity of integrated circuits increases so does the difficulty of creating efficient and high quality tests that can detect a variety of defect types that can occur throughout the manufacturing process. Three issues facing manufacturing test are the power consumed during testing, addressing different types of fault, and test data volume. In regards to the power consumed during testing, abnormal switching activity, far above that seen by functional operation, may occur due to the testing technique of scan insertion. While scan insertion greatly simplifies test generation for sequential circuits, it may lead to excessive switching activity due to the loading and unloading of scan data and when the scan cells are updated using functional clocks. This can potentially damage the circuit due to excessive heat or inadvertently fail a good circuit due to current supply demands beyond design specifications. Stuck-at tests detect when lines are shorted to either the power supply or ground. Open faults are broken connections within the circuit. Some open faults may not be detected by tests generated for stuck-at faults. Therefore tests may need to be generated in order to detect these open faults. The voltage on the open node is determined by circuit parameters. Due to the feature size of the circuit it may not be possible to determine these circuit parameters, making it very difficult or impossible to generate tests for open faults. Automated test equipment is used to apply test stimuli and observing the output response. The output response is compared to the known fault-free response in order to determine if it is faulty or fault-free. Thus, automated test equipment must store the test stimuli and the fault-free responses in memory. With increased integrated circuit complexity, the number of inputs, outputs, and faults increase, increasing the overall data required for testing. Automated test equipment is very expensive, proportional to the memory required to store the test stimuli and fault-free output response. Simply replacing automated test equipment is not cost effective. These issues in the manufacturing test of integrated circuits are addressed in this dissertation. First, a method to reduce power consumption in circuits which incorporate data volume reduction techniques is proposed. Second, a test generation technique for open faults which does not require knowledge of circuit parameters is proposed. Third, a technique to further reduce output data volume in circuits which currently incorporate output response compaction techniques is proposed. Experimental results for the three techniques show their effectiveness.

abstract: Gene circuit engineering facilitates the discovery and understanding of fundamental biology and has been widely used in various biological applications. In synthetic biology, gene circuits are often constructed by two main strategies: either monocistronic or polycistronic constructions. The Latter architecture can be commonly found in prokaryotes, eukaryotes, and viruses and has been largely applied in gene circuit engineering. In this work, the effect of adjacent genes and noncoding regions are systematically investigated through the construction of batteries of gene circuits in diverse scenarios. Data-driven analysis yields a protein expression metric that strongly correlates with the features of adjacent transcriptional regions (ATRs). This novel mathematical tool helps the guide for circuit construction and has the implication for the design of synthetic ATRs to tune gene expression, illustrating its potential to facilitate engineering complex gene networks. The ability to tune RNA dynamics is greatly needed for biotech applications, including therapeutics and diagnostics. Diverse methods have been developed to tune gene expression through transcriptional or translational manipulation. Control of RNA stability/degradation is often overlooked and can be the lightweight alternative to regulate protein yields. To further extend the utility of engineered ATRs to regulate gene expression, a library of RNA modules named degradation-tuning RNAs (dtRNAs) are designed with the ability to form specific 5’ secondary structures prior to RBS. These modules can modulate transcript stability while having a minimal interference on translation initiation. Optimization of their functional structural features enables gene expression level to be tuned over a wide dynamic range. These engineered dtRNAs are capable of regulating gene circuit dynamics as well as noncoding RNA levels and can be further expanded into cell-free system for gene expression control in vitro. Finally, integrating dtRNA with synthetic toehold sensor enables improved paper-based viral diagnostics, illustrating the potential of using synthetic dtRNAs for biomedical applications. / Dissertation/Thesis / Doctoral Dissertation Biomedical Engineering 2020

The interest in implementing energy-efficient digital circuits using micro and nanoelectromechanical resonator technology has increased significantly over the last decade given their lower energy consumption in comparison to complementary metal oxide-semiconductor circuits. In this thesis, multiple circuit designs based on micro and nanoelectromechanical beam resonators are presented. These circuits include a nano resonator-based flash style analog-to-digital converter, a 4-bit digital-to-analog converter, and a micro-resonator-based 7:3 counter, all among the key building blocks of a microcomputing system. Simulations and experimental results were obtained for all circuits. In general, the proposed circuits based on nanoelectromechanical resonators show up to 90% reduction in energy consumption compared to their complementary metal-oxide-semiconductor counterparts in MHz operation speeds, fulfilling requirements for many applications such as Internet of Things and biomedical devices.

This design covers the design of an integrated circuit (IC) in support of the active contact lens project at Cal Poly. The project aims to monitor intraocular eye pressure (IOP) to help diagnose and treat glaucoma, which is expected affect 6.3 million Americans by 2050. The IC is designed using IBM’s 130 nm 8RF process, is powered by an on-lens thin film 3.8 V rechargeable battery, and will be fabricated at no cost through MOSIS. The IC features a low-power linear regulator that powers a current-starved voltage-controlled oscillator (CSVCO) used for establishing a backscatter communication link. Additional circuitry is included to regulate power to and from the battery. An undervoltage lockout circuit protects the battery from deep discharge damage. When recharging, a rectifier and a voltage regulator provides overvoltage protection. These circuit blocks are biased primarily using a 696 mV subthreshold voltage reference that consumes 110.5 nA.

The main goal of this diploma thesis is to compare two circuits designed for LED powering with output current of units of Amperes. Both circuits are based on step-down converter topology, one with technology of synchronous rectifying and the other one without it. Calculations and selection of used components with real prototypes were made for both selected circuits. All selected components meet automotive qualification requirements for discrete products. Produced prototypes were compared in terms of functionality, efficiency, EMC and thermal radiation.

This diploma thesis is focused on the issue of pneumatic components testing and air leakage measurement. The current state of the given issue is summarized based on the analysis of leak testing methods in accordance with valid legislation. The aim of this thesis is to design methods for pneumatic components testing according to specification. As part of method verification, a pneumatic circuit with a pressure control system has been assembled, on which functionality tests of provided components and leak tests by the pressure-drop method have been performed. The results of these tests have been subsequently evaluated as consistent with the specification.