Thesis (M.E.)--University of Canterbury, 2009. / Typescript (photocopy). "June 2009." Includes bibliographical references (p. [107]-109). Also available via the World Wide Web.

published_or_final_version / Electrical and Electronic Engineering / Master / Master of Philosophy

Thesis (M. Phil.)--University of Hong Kong, 1998. / Includes bibliographical references.

University of Macau / Faculty of Science and Technology / Department of Electrical and Computer Engineering

This thesis presents the use of a Field Programmable Gate Array (FPGA) to control two Commercial-Off-The-Shelf (COTS) Power Electronic Building Blocks (PEBB) configured to produce a three-phase low distortion sine wave output. The next generation warship is expected to contain more electric loads that require quality variable frequency output. A typical propulsion motor in the 40MW range will probably require the current Total Harmonic Distortion to be less than 3% (MIL-STD-1399). However, high power low distortion inverters usually have associated high cost and weight penalties. This thesis presents a parallel hybrid converter which demonstrates the use of a high power low fidelity bulk inverter with a low power high fidelity active filter. The high power low fidelity output is sourced using a six-step inverter which produces the entire fundamental current. The low power hysteresis controlled active filter section produces only cancelling harmonic current. The paralleled result is a pristine output sine wave with a 1% current Total Harmonic Distortion (THD). This solution should offer the Navy a high fidelity high power inverter without the cost and weight penalties. / US Navy (USN) author.

The U. S. Navy is pursuing an all electric ship that will require enormous amounts of power for applications such as electric propulsion. Reliability and redundancy in the electronics are imperative, since failure of a critical system could leave a ship stranded and vulnerable. A parallel inverter drive topology has been proposed to provide reliability and redundancy through load sharing. The parallel architecture enables some functionality in the event that one of the inverters fails. This thesis explores paralleling current-mode inverters of different power levels and fidelities. A 50-kVA, three-phase hysteresis controlled inverter is designed, built, and tested at low power. The inverter is then tested in parallel with a low frequency, bulk inverter to demonstrate current sharing capability.

Thesis (M.S. in Electrical Engineering)--Naval Postgraduate School, September 2003. / Thesis advisor(s): Robert Ashton, Xiaoping Yun. Includes bibliographical references (p. 69-70). Also available online.

No description available.

Thesis (M.Eng.(Electrical, Electronic and Computer Engineering))--Universiteit van Pretoria, 2005. / Includes summary. Includes bibliographical references (leaves 256-261).

Thesis (M.S.)--University of Wisconsin--Madison, 1984. / Typescript. eContent provider-neutral record in process. Description based on print version record. Bibliogtsphy: leaves 118-119.