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Submitted by Emanuel Varela Cardoso (emanuel.varela@ufcg.edu.br) on 2018-09-21T17:18:48Z No. of bitstreams: 1 JOÃO HELDER GONZAGA MUNIZ DA SILVA - DISSERTAÇÃO (PPGEEI) 2016.pdf: 5964138 bytes, checksum: e0f1b793c6851d1c5ab1ec454862dfae (MD5) / Made available in DSpace on 2018-09-21T17:18:48Z (GMT). No. of bitstreams: 1 JOÃO HELDER GONZAGA MUNIZ DA SILVA - DISSERTAÇÃO (PPGEEI) 2016.pdf: 5964138 bytes, checksum: e0f1b793c6851d1c5ab1ec454862dfae (MD5) Previous issue date: 2016-11-14 / Os inversores multiníveis foram introduzidos como uma alternativa para o aumento da qualidade e da eficiência dos sistemas alimentados por inversores. Dependendo do nível de tensão c.c. do barramento aplicado ao inversor, pode ser inevitável a utilização de topologias multi-níveis. Estas topologias possibilitam a redução da tensão sobre cada um destes dispositivos. Contudo, uma quantidade maior de interruptores não só aumenta o custo final do inversor, como também requer o uso de estratégias mais complexas de modulação e controle. Ainda, alguns pontos inerentes aos inversores multiníveis como: redução da tensão de modo-comum, tolerância à faltas e desbalanceamento das tensões dos capacitores, entre outros, precisam ser investigados. Neste cenário, são de muito interesse os estudos de novas topologias multiníveis, além de novas técnicas de modulação simplificadas. Neste trabalho serão estudados inversores multiníveis com diferentes princípios de operação, abordando topologias híbridas formadas pelo empilhamento de células dois níveis. A primeira delas, consiste de um inversor monofásico de quatro níveis em ponte. Este inversor é composto de um braço de dois níveis e um braço de três níveis apresentando mesma tensão de bloqueio para todas as haves. Na segunda topologia, os pontos centrais de cada um dos braços são conectados ao mesmo ponto, com o braço externo envolvendo o interno, representando uma estrutura pouco investigada. Esta topologia necessita de chaves bidirecionais para tornar possível seu correto funcionamento. É feito ainda um estudo de um inversor de 2/3 níveis, onde é proposto um algoritmo de modulação simplificado, onde consegue-se uma significativa redução no número de operações realizados. Por fim, é estudado um inversor multinível simétrico híbrido baseado nas topologias meia-ponte e ANPC, onde são propostas duas alterações na topologia que juntamente com a modificação do padrão de chaveamento, fornece um melhor controle no balanceamento das tensões dos capacitores, além de reduzir a quantidade de fontes c.c. utilizadas pelo mesmo. / Multilevel inverters are an alternative for both quality and efficiency increase of inverter fed systems. Depending on the voltage level c.c. of the bus applied to the inverter, the usage of multilevel topologies is inevitable. Those topologies reduce the voltage over each of those devices. However, a higher quantity of switches increases the inverters final cost, and requires more complex approaches for control and modulation. Also, few inherent aspects of the multilevel inverters including: reduction of the common-mode voltage, fault tolerance and unbalance capacitors voltages, among other, need to be investigated. In this scenario, new multilevel topologies have great interest, also with new and simplified modulation techniques. In this work we study multilevel inverter with different operational principles, formed by formed by stacking two levels cells. The first one, consist of a single-phase inverter with a four level bridge. This inverter is composed of a two level leg and a three level leg, presenting the same blocking voltage for all the switches. In the second topology, every central point of each of the leg is connected into a common single point, with the extern leg over the intern one, a structure poorly studied. This topology needs bidirectional switches for a correct well function. A study of the 2/3 level inverter is done, in which a signicant redution of the operation numbers is a chieved. Finally, a hybrid symmetricmultilevel inverter is studied based on both half-bridge and ANPC topologies, in which two changes in the topology are proposed alongside with some changes in the switching standard. This provides a better control in the capacitors voltage balance, and reduces the amount of sources c.c. used by them.

Thesis submitted in fulfilment of the requirements for the degree Doctor of Technology: Electrical Engineering in the Faculty of Engineering at the Cape Peninsula University of Technology / This research focuses on the predictive current control of multilevel converters with the aim of providing an optimized system for three-phase, multilevel inverters (MLIs) so that the load current and the voltage of the capacitors can be controlled. A model predictive current control algorithm is proposed, specifically directed at the utilisation of power obtained from renewable energy systems (RESs). The model was developed for three-phase, multilevel voltage source inverters (MLVSIs), three-phase, three-level diode-clamped converters (DCCs) and flying capacitor converters (FCCs). In this study the renewable energy systems model is used to investigate system performance when power is supplied to a resistiveinductive load (RL-load). The proposed control method was split into two different control algorithms. Firstly, a finite set-model predictive current control (FS-MPCC) method was developed to control the output current of three-phase, MLIs. This control method was selected to reduce the calculation effort for model predictive control (MPC) and to increase the possible prediction horizon. Secondly, to solve the flying capacitor voltage balance problem in an FCC, as well as to solve the DC-link capacitor voltage balance problem in a DCC, a hysteresis-voltage alancing algorithm based on predictive control, was designed—this algorithm was used to keep the flying capacitor voltages and DC-link capacitor voltages within their hysteresis bands. Finally, for some classes of power converters, a performance evaluation of the FS-MPCC method for three-phase, three-level MLIs was investigated in terms of power quality and dynamic response. The improvement was assessed in terms of total harmonic distortion (THD) of the output voltage for the RL-load. The modelling and co-simulation were carried out using MATLAB/Simulink with PSIM software. The co-simulation results indicated that the proposed control algorithms achieved both high performance and a high degree of robustness in RESs applications.

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Indiana University-Purdue University Indianapolis (IUPUI) / This thesis deals with three phase inverters and the different control strategies that can be associated with an inverter being used together. The first part of this thesis discusses the present research in the fields of PV panels, motor drive systems and three phase inverters along with their control. This control includes various strategies like MPPT, Volts-Hertz and modulation index compensation. Incorporating these techniques together is the goal of this thesis. A new topology for operating an open end motor drive system has also been discusses, where a boost converter and a flyback converter have been used in cascade to run a three phase motor. The main advantage of this is increasing the number of levels and improving the quality of the output voltage, not to mention a few other benefits of having the proposed circuit. A new algorithm has also been designed for starting and stopping the motor, which controls the current drawn from the power source during starting.

Multilevel voltage source inverters have been receiving more and more attention from the industry and academia as a choice for high voltage and high power applications. The high voltage multilevel inverters can be constructed with existing low voltage semiconductor switches, which already have a mature technology for handling low voltages, thus improving the reliability of the overall inverter system. These multilevel inverters generate the output voltage in the form of multi-stepped waveform with smaller amplitude. This will result in less dv/dt at the motor inputs and electromagnetic interference (EMI) caused by switching is considerably less. Because of the multi-stepped waveform, the instantaneous error in the output voltage will be always less compared to the conventional two-level inverter output voltage. It will reduce the unwanted harmonic content in the output voltage, which will enable to switch the inverter at lower frequencies. Many interesting multi level inverter topologies are proposed by various research groups across the world from industry and academic institutions. But apart from the conventional 3-level NPC and H-bridge topology, others are not yet highly preferred for general high power drives applications. In this respect, two different five-level inverter topologies and one three-level inverter topology for high power induction motor drive applications are proposed in this work. Existing knowledge from published literature shows that, the three-level voltage space vector diagram can be generated for an open-end winding induction motor by feeding the motor phase windings with two two-level inverters from both sides. In such a configuration, each inverter is capable of assuming 8 switching states independent of the other. Therefore a total of 64 switching combinations are possible, whereas the conventional NPC inverter have 27 possible switching combinations. The main drawback for this configuration is that, it requires a harmonic filter or isolated voltage source to suppress the common mode currents through the motor phase winding. In general, the harmonic filters are not desirable because, it is expensive and bulky in nature. Some topologies have been presented, in the past, to suppress the common mode voltage on the motor phase windings when the both inverters are fed with a single voltage source. But these schemes under utilize the dc-link voltage or use the extra power circuit. The scheme presented in chapter-3 eliminates the requirement of harmonic filter or isolated voltage source to block the common mode current in the motor phase windings. Both the two-level inverters, in this scheme, are fed with the same voltage source with a magnitude of Vdc/2 where Vdc is the voltage magnitude requires for the NPC three-level inverter. In this scheme, the identical voltage profile winding coils (pole pair winding coils), in the four pole induction motor, are disconnected electrically and reconnected in two star groups. The isolated neutrals, provided by the two star groups, will not allow the triplen currents to flow in the motor phase windings. To apply identical fundamental voltage on disconnected pole pair winding, decoupled space vector PWM is used. This PWM technique eliminates the first center band harmonics thereby it will allow the inverters to operate at lower switching frequency. This scheme doesn’t require any additional power circuit to block the triplen currents and also it will not underutilize the dc-bus voltage. A five-level inverter topology for four pole induction motor is presented in chapter-3. In this topology, the disconnected pole pair winding coils are effectively utilized to generate a five-level voltage space vector diagram for a four pole induction motor. The disconnected pole pair winding coils are fed from both sides with conventional two-level inverters. Thereby the problems like capacitor voltage balancing issues are completely eliminated. Three isolated voltage sources, with a voltage magnitude of Vdc/4, are used to block the triplen current in the motor phase windings. This scheme is also capable of generating 61 space vector locations similar to conventional NPC five-level inverter. However, this scheme has 1000 switching combinations to realize 61 space vector locations whereas the NPC five-level inverter has 125 switching combinations. In case of any switch failure, using the switching state redundancy, the proposed topology can be operated as a three-level inverter in lower modulation index. But this topology requires six additional bi-directional switches with a maximum voltage blocking capacity of Vdc/8. However, it doesn’t require any complicated control algorithm to generate the gating pulses for bidirectional switches. The above presented two schemes don’t require any special design modification for the induction machine. Although the schemes are presented for four pole induction motor, this technique can be easily extend to the induction motor with more than four poles and thereby the number of voltage levels on the phase winding can be further increased. An alternate five-level inverter topology for an open-end winding induction motor is presented in chapter-4. This topology doesn’t require to disconnect the pole pair winding coils like in the previous propositions. The open-end winding induction motor is fed from one end with a two-level inverter in series with a capacitor fed H-bridge cell, while the other end is connected to a conventional two-level inverter to get a five voltage levels on the motor phase windings. This scheme is also capable of generating a voltage space vector diagram identical to that of a conventional five-level inverter. A total of 2744 switching combinations are possible to generate the 61 space vector locations. With such huge number switching state redundancies, it is possible to balance the H-bridge capacitor voltage for full modulation range. In addition to that, the proposed topology eliminates eighteen clamping diode having different voltage ratings compared to the NPC inverter. The proposed topology can be operated as a three-level inverter for full modulation range, in case of any switch failure in the capacitor fed H-bridge cell. All the proposed topologies are experimentally verified on a 5 h.p. four pole induction motor using V/f control. The PWM signals for the inverters are generated using the TMS320F2812 and GAL22V10B/SPARTAN XC3S200 FPGA platforms. Though the proposed inverter topologies are suggested for high-voltage and high-power industrial IM drive applications, due to laboratory constraints the experimental results are taken on the 5h.p prototypes. But all the proposed schemes are general in nature and can be easily implemented for high-voltage high-power drive applications with appropriate device ratings.

Master of Science / Department of Electrical and Computer Engineering / Behrooz Mirafzal / Wide bandgap devices have gained increasing attention in the market of power electronics for their ability to perform even in harsh environments. The high voltage blocking and high temperature withstanding capabilities make them outperform existing Silicon devices. They are expected to find places in future traction systems, electric vehicles, LED lightning and renewable energy engineering systems. In spite of several other advantages later mentioned in this paper, WBG devices also face a few challenges which need to be addressed before they can be applied in large scale in industries. Electromagnetic interference and new requirements in packaging methods are some of the challenges being faced by WBG devices. After the commercialization of these devices, many experiments are being carried out to understand and validate their abilities and drawbacks. This paper summarizes the experimental results of various applications of mainly Silicon Carbide (SiC) and Gallium Nitride (GaN) power devices and also includes a section explaining the current challenges for their employment and improvements being made to overcome them.

Este trabalho apresenta o desenvolvimento de uma metodologia para a etiquetagem e qualificação de inversores para Sistemas Fotovoltaicos Conectados à Rede, com finalidade de servir de proposta de procedimento para inclusão no Regulamento de Avaliação de Conformidade de Equipamentos e Sistemas Fotovoltaicos do Programa Brasileiro de Etiquetagem. O procedimento desenvolvido avalia os inversores quanto à eficiência, qualidade de energia, proteções e informações operacionais e de instalação. / This work presents the development of a methodology for qualification and labeling of inverters for grid-connected photovoltaic systems, aiming serving as procedural proposal for inclusion in the Conformity Assessment Rules of Equipments and Photovoltaic Systems of the Brazilian Labeling Program. The developed procedure evaluates the inverters efficiency, power quality, protections and operational and installation information.

Cargas e fontes elétricas de pequeno porte, integradas através de alimentadores de distribuição de baixa tensão, agrupadas e gerenciadas de tal maneira que se comportem como uma única entidade controlável dentro de um sistema de potência e com a capacidade de operar de forma paralela ou isolada da rede elétrica convencional, constituem-se em um novo tipo de sistema elétrico conhecido como Minirrede. Esta tese aborda o problema relacionado à estabilidade dinâmica de Minirredes com controle autônomo de frequência e tensão, quando operadas de forma isolada da rede convencional. As minirredes analisadas são compostas por combinações de fontes elétricas convencionais e fontes alternativas que não geram naturalmente em 50 ou 60 Hz, sendo necessária a utilização de inversores para sua conexão com a rede elétrica. A análise se realiza no espaço de estados com metodologias baseadas nas teorias que envolvem os autovalores e autovetores da matriz de estado. Para isto, modelos no espaço de estados são desenvolvidos para cada componente da Minirrede, mantendo um compromisso entre precisão e complexidade. O caráter analítico da análise permite investigar a relação entre a estabilidade da Minirrede e os parâmetros do sistema, tais como ganhos dos controladores, dimensionamento da rede, configurações de geração, entre outros. Análises complementares de sensibilidade dos autovalores aos parâmetros elétricos do sistema permitem inferir o comportamento dinâmico de diversas configurações de Minirredes, obtendo-se importantes conclusões à respeito. Os resultados analíticos são verificados através de simulação computacional no ambiente Simulink/Matlab®. / Electrical loads and small power sources, integrated through low voltage distribution feeders, managed in such a way to behave as one controllable entity within in a power system, and with the ability to operate connected or non-connected to the conventional power system is a new kind of electrical system known as Microgrid. This thesis addresses the problem related to dynamic stability of island Microgrids with autonomous control of frequency and voltage. The Microgrids analyzed are composed of combinations of conventional and alternative power sources that do not generate electricity naturally in 50 or 60 Hz, therefore inverters are needed to provide AC network interface. The analysis is performed in the state space with methodologies based on theories involving the eigenvalues and eigenvectors of the state matrix. For this, state-space models are developed for each component of Microgrid, maintaining a compromise between accuracy and complexity. The analytical nature of this study allows investigating the relationship between the stability of Microgrid and parameters of the system, such as controller gains, network design, generation architectures, among others. Complementary sensitivity analyzes of eigenvalues to the electrical parameters of the system allow us to infer the dynamic behavior of various configurations of Microgrids, obtaining important conclusions on the matter. The analytical results are verified by computer simulation using the platform Simulink/Matlab®.

CoordenaÃÃo de AperfeiÃoamento de Pessoal de NÃvel Superior / This work presents a comparative evaluation of three single-phase neutral point clamped multilevel inverters, based on switching cells, which have as a common characteristic the capacity increase of the total output current of the converters without increasing the current efforts in semiconductors. The technique employed to perform this evaluation consists primarily on individual analysis of the classical three level topology, applying only the parallelism of switching cells. Then a detailed analysis of the main topology evaluated in this work is performed. It is the five level neutral point clamped inverter, based on multi-state switching cell, which uses multilevel interleaved converters, coupled magnetically through an autotransformer in order to distribute uniformly the total output current between their windings, and consequently between the semiconductors of the converter. In addition to presenting reduced conduction losses in the semiconductors, this technique also provides a reduction in volume and weight of magnetic components due to frequency of operation of reactive elements is a multiple of the switching frequency of the switches. Consequently, the resulting converters present high efficiency, high power density and low harmonic distortion for the output voltage and output current. The theoretical analysis of the five level neutral point clamped inverter, based on multi-state switching cell, is verified by digital simulation and by 5 kW prototypes experimentation. Simulation and experimental results are also presented for the third topology analyzed, the five level neutral point clamped inverter, based on interleaved switching cells. Finally, a comparative evaluation is performed for the three inverters analyzed. / Este trabalho apresenta a avaliaÃÃo comparativa de trÃs inversores multinÃveis monofÃsicos com grampeamento do ponto central, baseados em cÃlulas de comutaÃÃo, que apresentam como caracterÃstica comum a elevaÃÃo da capacidade da corrente total de saÃda dos conversores sem aumentar os esforÃos de corrente nos semicondutores. A tÃcnica utilizada para realizar esta avaliaÃÃo consiste, primeiramente, na anÃlise individual da topologia clÃssica de trÃs nÃveis, aplicando apenas o paralelismo de cÃlulas de comutaÃÃo. Em seguida à realizada a anÃlise detalhada da principal topologia avaliada neste trabalho. Trata-se do inversor de cinco nÃveis com grampeamento do ponto central, baseado na cÃlula de comutaÃÃo de mÃltiplos estados, que utiliza conversores multinÃveis intercalados, acoplados magneticamente atravÃs de um autotransformador que, por sua vez, tem como finalidade distribuir uniformemente a corrente total de saÃda entre os enrolamentos e, consequentemente, entre os semicondutores do conversor. AlÃm de apresentar perdas de conduÃÃo reduzidas nos semicondutores, este conversor tambÃm apresenta uma reduÃÃo no volume e peso dos componentes magnÃticos, devido à frequÃncia de operaÃÃo dos elementos passivos possuir um valor mÃltiplo da frequÃncia de comutaÃÃo dos interruptores. Como consequÃncia, os conversores resultantes apresentam alto rendimento, alta densidade de potÃncia e uma baixa distorÃÃo harmÃnica total para a tensÃo e corrente de saÃda. A anÃlise teÃrica do inversor de cinco nÃveis com grampeamento do ponto central, baseado na cÃlula de comutaÃÃo de mÃltiplos estados, à verificada atravÃs de simulaÃÃo computacional e da experimentaÃÃo obtida a partir de protÃtipos desenvolvidos para uma potÃncia de 5 kW. SÃo tambÃm apresentados resultados de simulaÃÃo e experimentais para a terceira topologia analisada, o inversor de cinco nÃveis com grampeamento do ponto central, baseado em cÃlulas de comutaÃÃo intercaladas. Finalmente, à realizada uma avaliaÃÃo comparativa entre os trÃs inversores analisados.