This thesis deals with a new solution for medium voltage drives. Load Commutated Inverter (LCI) fed synchronous motor drive is a popular solution for high power drive applications. Though the induction machine is more rugged and cheaper compared to the synchronous machine, LCI fed induction motor drive solution is not available. The basic advantage of a synchronous machine over an induction machine is the fact that the synchronous machine can operate at leading power factor. Due to this property load commutation of SCR switches of the LCI is achievable for synchronous machine. On the contrary an induction machine always draws lagging power factor current; this makes it unsuitable as a drive motor for LCI technology. In this thesis a new LCI fed induction motor drive configuration is developed as an alternative for synchronous motor drives. A new variant of six phase induction motor is proposed in this context. The machine is named as Active Reactive Induction Machine (ARIM). The ARIM contains two sets of three-phase windings with isolated neutral. Both the windings have a common axis. One winding carries the active power and can be wound for higher voltage (say 11kV). The other winding supplies the total reactive power of the machine and can be wound for lower voltage (say 2.2 kV). The rotor is a standard squirrel cage. High power induction machines usually demand lesser magnitude of reactive power compared to the total power rating of the machine ( 20% ). Therefore excitation winding has a smaller fraction of the total machine rating compared to the power winding. A VSI with an LC filter supplies reactive power to the ARIM through the excitation winding and ensures leading power factor at the power winding. This is similar to the excitation control of the LCI fed synchronous machine. The direct VSI connection is possible due to the lower voltage rating for the excitation winding. In this way, the VSI voltage rating does not limit the highest motor voltage that can be handled. An LCI supplies the real power into the ARIM from the power winding. The LCI currents are quasi square wave in shape. Therefore they have rich low order harmonic content. They cause 6th and 12th harmonic torque pulsations in the machine. This is a problem for the LCI fed synchronous machine drive. In the proposed drive, the VSI can compensate these low frequency m.m.f. harmonics inside the machine air gap to remove torque pulsation and rotor harmonic losses. The advantage of the proposed topology is that no transformer is required to drive an 11kV machine. It is always desirable to feed sinusoidal voltage and current to both the power winding and the excitation winding. To address this problem, a second configuration is proposed. A low power three-level VSI is connected in shunt at the power winding with the proposed ARIM drive as discussed above. This VSI compensates the low frequency harmonic currents to achieve sinusoidal motor currents at the motor winding. This VSI acts as a shunt active filter and compensates for the lower order harmonics injected by the LCI. The proposed topologies have LC filters to maintain sinusoidal motor voltages and currents by absorbing the VSI switching frequency components. But the motor terminal voltage oscillates at system resonant frequency due to the presence of LC filters. These resonant components in the terminal voltages are required to be eliminated for smooth terminal voltages and safe load commutation of the thyristors. In this thesis a simple active damping method is proposed to mitigate these issues. The proposed topologies are experimentally verified with an ARIM with 415 V power winding and 220 V excitation winding. The control is carried out on a digital platform having a TMS 320LF 2407A DSP processor and an ALTERA CYCLONE FPGA processor. Results from the prototype experimental drive are presented to show the feasibility and performance of the proposed drive configurations.

No description available.

No description available.

The inverter dead-time is integral to the safety of a voltage source inverter (VSI). Dead-time is introduced between the complementary gating signals of the top and bottom switches in each VSI leg to prevent shoot-through fault. This thesis reports and investigates dead-time induced sub-harmonic oscillations in open-loop induction motor drives of different power levels, under light-load conditions. The thesis develops mathematical models that help understand and predict the oscillatory behaviour of such motor drives due to dead-time act. Models are also developed to study the impact of under-compensation and over-compensation of dead-time act on stability. The various models are validated through extensive simulations and experimental results. The thesis also proposes and validates active damping schemes for mitigation of such sub-harmonic oscillations. The thesis reports high-amplitude sub-harmonic oscillations in the stator current, torque and speed of a 100-kW open-loop induction motor drive in the laboratory, operating under no-load. Experimental studies, carried out on 22-kW, 11-kW, 7.5-kW and 3.7-kW open-loop induction motor drives, establish the prevalence of dead-time induced sub-harmonic oscillations in open-loop motor drives of different power levels. An experimental procedure is established for systematic study of this phenomenon in industrial drives. This procedure yields the operating region, if any, where the motor drive is oscillatory. As a first step towards understanding the oscillatory behaviour of the motor drive, a mathematical model of the VSI is derived in a synchronously revolving reference frame (SRF), incorporating the of dead-time on the inverter output voltage. This leads to a modified dynamic model of the inverter-fed induction motor in the SRF, inclusive of the dead-time act. While the rotor dynamic equations are already non-linear, dead-time is found to introduce nonlinearities in the stator dynamic equations as well. The nonlinearities in the modified dynamic model make even the steady solution non-trivial. Under steady conditions, the dead-time can be modelled as the drop across an equivalent resistance (Req0) in the stator circuit. A precise method to evaluate the equivalent resistance Req0 and a simple method to arrive at the steady solution are proposed and validated. For the purpose of stability analysis, a small-signal model of the drive is then derived by linearizing the non-linear dynamic equations of the motor drive, about a steady-state operating point. The proposed small-signal model shows that dead-time contributes to different values of equivalent resistances along the q-axis and d-axis and also to equivalent cross-coupling reactance’s that appear in series with the stator windings. Stability analysis performed using the proposed model brings out the region of oscillatory behaviour (or region of small-signal instability) of the 100-kW motor drive on the voltage versus frequency (V- f) plane, considering no-load. The oscillatory region predicted by the small-signal analysis is in good agreement with simulations and practical observations for the 100-kW motor drive. The small-signal analysis is also able to predict the region of oscillatory behaviour of an 11-kW motor drive, which is con consumed by simulations and experiments. The analysis also predicts the frequencies of sub-harmonic oscillations at different operating points quite well for both the drives. Having the validity of the small-signal analysis at different power levels, this analytical procedure is used to predict the regions of oscillatory behaviour of 2-pole, 4-pole, 6-pole and 8-pole induction motors rated 55 kW and 110 kW. The impact of dead-time on inverter output voltage has been studied widely in literature. This thesis studies the influence of dead-time on the inverter input current as well. Based on this study, the dynamic model of the inverter fed induction motor is extended to include the dc-link dynamics as well. Simulation results based on this extended model tally well with the experimentally measured dc-link voltage and stator current waveforms in the 100-kW drive. Dead-time compensation may be employed to mitigate the dead-time and oscillatory behaviour of the drive. However, accurate dead-time compensation is challenging to achieve due to various factors such as delays in gate drivers, device switching characteristics, etc. Effects of under-compensation and over-compensation of dead time are investigated in this thesis. Under-compensation is shown to result in the same kind of oscillatory behaviour as observed with dead-time, but the fundamental frequency range over which such oscillations occur is reduced. On the other hand, over-compensation of dead-time effect is shown to result in a different kind of oscillatory behaviour. These two types of oscillatory behaviour due to under- and over-compensation, respectively, are distinguished and demonstrated by analyses, simulations and experiments on the 100-kW drive. To mitigate the oscillatory behaviour of the drive, an active damping scheme is proposed. This scheme emulates the effect of an external inductor in series with the stator winding. A small-signal model is proposed for an induction motor drive with the proposed active damping scheme. Simulations and experiments on the 100-kW drive demonstrate effective mitigation of light-load instability with this active damping scheme. In the above inductance emulation scheme, the emulated inductance is seen by the sub-harmonic components, fundamental component as well as low-order harmonic components of the motor current. Since the emulated inductance is also seen by the fundamental component, there is a fundamental voltage drop across the emulated inductance, leading to reduced co-operation of the induction motor. Hence, an improved active damping scheme is proposed wherein the emulated inductance is seen only by the sub-harmonic and low-order harmonic components. This is achieved through appropriate altering in the synchronously revolving domain. The proposed improved active damping scheme is shown to mitigate the sub-harmonic oscillation effectively without any reduction in flux.

This thesis analyses, develops and implements a very fast on-line parameter identification algorithm for both rotor and stator resistances of a rotor flux oriented induction motor drive, with the best possible convergence results using artificial neural networks and fuzzy logic systems. The thesis focuses mainly on identifying the rotor resistance, which is the most critical parameter for RFOC. Limitations of PI and fuzzy logic based estimators were identified. Artificial neural network based estimators were found to track the rotor and stator resistances of the drive accurately and fast. The rotor flux of the induction motor estimated with a classical voltage model was the key input of the rotor resistance estimator. Because, pure digital integrators were unable to play this role, an alternative rotor flux synthesizer using a programmable cascaded filter was developed. This rotor flux synthesizer has been used for all of the resistance estimators. It was found that the error in rotor resistance estimation using an ANN was contributed to by error in the stator resistance (caused by motor heating). Several stator resistance estimators using the stator current measurements were developed. The limitations of a PI and a fuzzy estimator for stator resistance estimation were also established. A new stator resistance identifier using an ANN was found to be much superior to the PI and fuzzy estimators, both in terms of dynamic estimation times and convergence problems. The rotor resistance estimator developed for this thesis used a feedforward neural network and the stator resistance estimator used a recurrent neural network. Both networks exhibited excellent learning capabilities; the stator resistance estimator network was very fast as it had a feedback input. A speed estimator was also developed with the state estimation principles, with the updated motor parameters supplied by the ANN estimators. Analysis for speed sensorless operation has shown that the stator and rotor resistances could be updated on-line.

No description available.

No description available.

A split-phase induction motor (SPIM) is obtained by splitting each of the three-phase stator windings of an induction motor into two equal halves. This results in two sets of three-phase windings with a spatial angle difference of 30◦ (electrical) between them. The two sets of windings are fed from two different voltage-source inverters for speed control of the split-phase motor drive. Low dc bus voltage requirement and improved torque profile are some of the advantages of the split-phase motor, compared to the normal three-phase induction motor. A pulse width modulation (PWM) technique is used to produce the gating signals for the power semiconductor devices in the two inverters. The PWM technique can either be a carrier comparison (CC) based method or a space-vector (SV) based scheme. The carrier based PWM methods employ six modulating waves, which are compared against a common triangular carrier to generate the gating pulses. In space-vector based PWM schemes, the voltage reference is specified in terms of a rotating reference vector. In each subcycle, a set of voltage vectors are applied for appropriate durations of time to produce an average vector equal to the reference vector. Unlike three-phase induction motor drives, where the voltage vectors are two dimensional, the voltage vectors in the case of SPIM drive are four dimensional. This thesis presents a detailed survey on carrier-comparison based and space-vector based PWM techniques for the SPIM drive. In this thesis, sine-triangle PWM (STPWM) is analyzed from a space-vector perspective. The set of voltage vectors applied and the sequence of application of the voltage vectors in each half-carrier cycle are studied. The analysis shows that the set of voltage vectors and the switching sequence employed by STPWM are different from those used by the well known SVPWM tech-niques. Two other CC based PWM techniques, based on common mode injection, are considered for the SPIM drive. In one method, the common-mode signal is derived from all the six modulating signals, and is the same for both the inverters. In the second method, the common-mode signal is different for the two inverters; each common-mode signal is derived from the three-phase sinusoidal signals of the respective inverter. The study shows that the latter method has the highest dc bus utilization and results in the lowest total harmonic distortion (THD) among the CC PWM techniques. An experimental comparison of the three carrier-comparison techniques with three well known space-vector PWM techniques is presented. Total harmonic distortion (THD) of the line current is measured at different modulation indices for all six techniques. The experimental results are obtained from a 6kW, 200V, 50Hz split-phase induction motor drive, with constant V /F ratio. The PWM techniques are implemented using an ALTERA cyclone II field programmable gate array (FPGA) digital controller. One of the SV techniques, termed here as 4-dimensional 24-sector (4D24SEC) PWM is found to be the best in terms of line current THD among all the CC and SV based PWM techniques considered. However, compared to any carrier-based technique, implementation of the 4D24SEC PWM based on the space vector approach is found to be resource intensive. Hence, an equivalent carrier-based implementation of 4D24SEC PWM is proposed in this thesis. The feasibility of the proposed approach is verified experimentally, and is found to be consuming much less logical resources than the space-vector implementation (i.e. 4102 logical elements for the CC approach as against 33,655 logical elements for the SV approach). A new space-vector PWM technique is also proposed in the thesis. This technique utilizes a new set of voltage vectors and a new switching sequence, which are motivated by the analyses of the carrier-based methods, presented earlier. The proposed technique is implemented, and is compared with other space-vector and carrier-based methods at different modulation indices and switching frequencies. The proposed PWM technique is found to have the same dc-bus utilization as the existing 4-dimensional SV based PWM techniques. The performance of the proposed method is found to be not better than existing 4-dimensional SV PWM methods. The possibilities for new switching sequence is being explored here.

Current-Controlled Pulse Width Modulated (CC-PWM) Voltage Source Inverters (VSIs) are extensively employed in high performance drives (HPD) because of the considerable advantages offered by them, such as, excellent dynamic response and inherent over-current protection, as compared to the voltage-controlled PWM (VC-PWM) VSIs. Amongst the different types of CC-PWM techniques, hysteresis current controllers offer significant simplicity in implementation. However, conventional type of hysteresis controllers (with independent comparators) suffers from some well-known drawbacks, such as, limit cycle oscillations (especially at lower speeds of operation of machine), overshoot in current error, generation of sub-harmonic components in the current, and random (non-optimum) switching of inverter voltage vectors. Common problems associated with the conventional, as well as current error space phasor based hysteresis controllers with fixed bands (boundary), are the wide variation of switching frequency in the fundamental output cycle and variation of switching frequency with the change in speed of the load motor. These problems cause increased switching losses in the inverter, non-optimum current ripple, excess harmonics in the load current and subsequent additional machine heating. A continuously varying parabolic boundary for the current error space phasor is proposed previously to get the switching frequency variation pattern of the output voltage of the hysteresis controller based PWM inverter similar to that of voltage controlled space vector PWM (VC SVPWM) based VSI. But the major problem associated with this technique is the requirement of two outer parabolas outside the current error space phasor boundary for the identification of sector change which gives rise to some switching frequency variations in one fundamental cycle and over the entire operating speed range. It also introduces 5th and 7th harmonic components in the voltage causing 5th and 7th harmonic currents in the induction motor. These harmonic currents causes 6th harmonic torque pulsations in the machine. This thesis proposes a new technique which replaces the outer parabolas and uses current errors along orthogonal axes for detecting the sector change, so that a fast and accurate detection of sector change is possible. This makes the voltage harmonic spectrum of the proposed hysteresis controller based inverter exactly matching with that of a constant switching frequency SVPWM based inverter. This technique uses the property that the current error along one of the orthogonal axis changes its direction during sector change. So the current error never goes outside the parabolic boundary as in the case of outer parabolas based sector change technique. So the proposed new technique for sector change eliminates the 5th and 7th harmonic components from the applied voltage and thus eliminates the 5th and 7th harmonic currents in the motor. So there will be no introduction of 6th harmonic torque pulsations in the motor. Using the proposed scheme for sector change and parabolic boundary for current error space phasor, simulation study was carried out using Matlab-Simulink. Simulation study showed that the switching frequency variations in a fundamental cycle and over the entire speed range of the machine upto six step mode operation is similar to that of a VC-SVPWM based VSI. The proposed hysteresis controller is experimentally verified on a 3.7 kW IM drive fed with a two-level VSI using vector control. The proposed current error space phasor based hysteresis controller providing constant switching frequency is completely implemented on the TI TMS320LF2812 DSP controller platform. The three-phase reference currents are generated depending on the frequency command and the controller is tested with drive for the entire operating speed range of the machine in forward and reverse directions. Steady state and transient results of the proposed drive are presented in this thesis. This thesis also proposes a new hysteresis controller which eliminates parabolic boundary and replaces it with a simple online computation of the boundary. In this proposed new hysteresis controller the boundary computed in the present sampling interval is used for identifying next vector to be switched. This thesis gives a detailed mathematical explanation of how the boundary is computed and how it is used for selecting vector to be switched in a sector. It also explains how the sector in which stator voltage vector is present is determined. The most important part of this proposed hysteresis controller is the estimation of stator voltages along alpha and beta axes during active and zero vector periods. Estimation of stator voltages are carried out using current errors along alpha and beta axes and steady state equivalent circuit of induction motor. Using this estimated stator voltages along alpha and beta axes, instantaneous phase voltages are computed and used for finding individual voltage vector switching times. These switching times are used for the computation of hysteresis boundary for individual vectors. So the hysteresis boundary for individual vectors are exactly calculated and used for vector change detection, making phase voltage harmonic spectrum exactly similar to that of constant switching frequency VC SVPWM inverter. Sector change detection is very simple, since we have the estimated stator voltages along alpha and beta axes to give exact position of stator voltage vector. Simulation study to verify the steady state as well as transient performance of the proposed controller based VSI fed IM drive is carried out using Simulink tool box of Matlab Simulation Software. The proposed hysteresis controller is experimentally verified on a 3.7 kW IM drive fed with a two-level VSI using vector control. The proposed current error space phasor based hysteresis controller providing constant switching frequency profile for phase voltage is implemented on the TI TMS320LF2812 DSP controller platform. The three-phase reference currents are generated depending on the frequency command and the proposed hysteresis controller is tested with drive for the entire operating speed range of the machine in forward and reverse directions. Steady state and transient results of the proposed drive are presented for different operating conditions.

Multilevel voltage source inverters have been receiving more and more attention from the industry and academia as a choice for high voltage and high power applications. The high voltage multilevel inverters can be constructed with existing low voltage semiconductor switches, which already have a mature technology for handling low voltages, thus improving the reliability of the overall inverter system. These multilevel inverters generate the output voltage in the form of multi-stepped waveform with smaller amplitude. This will result in less dv/dt at the motor inputs and electromagnetic interference (EMI) caused by switching is considerably less. Because of the multi-stepped waveform, the instantaneous error in the output voltage will be always less compared to the conventional two-level inverter output voltage. It will reduce the unwanted harmonic content in the output voltage, which will enable to switch the inverter at lower frequencies. Many interesting multi level inverter topologies are proposed by various research groups across the world from industry and academic institutions. But apart from the conventional 3-level NPC and H-bridge topology, others are not yet highly preferred for general high power drives applications. In this respect, two different five-level inverter topologies and one three-level inverter topology for high power induction motor drive applications are proposed in this work. Existing knowledge from published literature shows that, the three-level voltage space vector diagram can be generated for an open-end winding induction motor by feeding the motor phase windings with two two-level inverters from both sides. In such a configuration, each inverter is capable of assuming 8 switching states independent of the other. Therefore a total of 64 switching combinations are possible, whereas the conventional NPC inverter have 27 possible switching combinations. The main drawback for this configuration is that, it requires a harmonic filter or isolated voltage source to suppress the common mode currents through the motor phase winding. In general, the harmonic filters are not desirable because, it is expensive and bulky in nature. Some topologies have been presented, in the past, to suppress the common mode voltage on the motor phase windings when the both inverters are fed with a single voltage source. But these schemes under utilize the dc-link voltage or use the extra power circuit. The scheme presented in chapter-3 eliminates the requirement of harmonic filter or isolated voltage source to block the common mode current in the motor phase windings. Both the two-level inverters, in this scheme, are fed with the same voltage source with a magnitude of Vdc/2 where Vdc is the voltage magnitude requires for the NPC three-level inverter. In this scheme, the identical voltage profile winding coils (pole pair winding coils), in the four pole induction motor, are disconnected electrically and reconnected in two star groups. The isolated neutrals, provided by the two star groups, will not allow the triplen currents to flow in the motor phase windings. To apply identical fundamental voltage on disconnected pole pair winding, decoupled space vector PWM is used. This PWM technique eliminates the first center band harmonics thereby it will allow the inverters to operate at lower switching frequency. This scheme doesn’t require any additional power circuit to block the triplen currents and also it will not underutilize the dc-bus voltage. A five-level inverter topology for four pole induction motor is presented in chapter-3. In this topology, the disconnected pole pair winding coils are effectively utilized to generate a five-level voltage space vector diagram for a four pole induction motor. The disconnected pole pair winding coils are fed from both sides with conventional two-level inverters. Thereby the problems like capacitor voltage balancing issues are completely eliminated. Three isolated voltage sources, with a voltage magnitude of Vdc/4, are used to block the triplen current in the motor phase windings. This scheme is also capable of generating 61 space vector locations similar to conventional NPC five-level inverter. However, this scheme has 1000 switching combinations to realize 61 space vector locations whereas the NPC five-level inverter has 125 switching combinations. In case of any switch failure, using the switching state redundancy, the proposed topology can be operated as a three-level inverter in lower modulation index. But this topology requires six additional bi-directional switches with a maximum voltage blocking capacity of Vdc/8. However, it doesn’t require any complicated control algorithm to generate the gating pulses for bidirectional switches. The above presented two schemes don’t require any special design modification for the induction machine. Although the schemes are presented for four pole induction motor, this technique can be easily extend to the induction motor with more than four poles and thereby the number of voltage levels on the phase winding can be further increased. An alternate five-level inverter topology for an open-end winding induction motor is presented in chapter-4. This topology doesn’t require to disconnect the pole pair winding coils like in the previous propositions. The open-end winding induction motor is fed from one end with a two-level inverter in series with a capacitor fed H-bridge cell, while the other end is connected to a conventional two-level inverter to get a five voltage levels on the motor phase windings. This scheme is also capable of generating a voltage space vector diagram identical to that of a conventional five-level inverter. A total of 2744 switching combinations are possible to generate the 61 space vector locations. With such huge number switching state redundancies, it is possible to balance the H-bridge capacitor voltage for full modulation range. In addition to that, the proposed topology eliminates eighteen clamping diode having different voltage ratings compared to the NPC inverter. The proposed topology can be operated as a three-level inverter for full modulation range, in case of any switch failure in the capacitor fed H-bridge cell. All the proposed topologies are experimentally verified on a 5 h.p. four pole induction motor using V/f control. The PWM signals for the inverters are generated using the TMS320F2812 and GAL22V10B/SPARTAN XC3S200 FPGA platforms. Though the proposed inverter topologies are suggested for high-voltage and high-power industrial IM drive applications, due to laboratory constraints the experimental results are taken on the 5h.p prototypes. But all the proposed schemes are general in nature and can be easily implemented for high-voltage high-power drive applications with appropriate device ratings.