Thesis submitted in fulfilment of the requirements for the degree Doctor of Technology: Electrical Engineering in the Faculty of Engineering at the Cape Peninsula University of Technology / This research focuses on the predictive current control of multilevel converters with the aim of providing an optimized system for three-phase, multilevel inverters (MLIs) so that the load current and the voltage of the capacitors can be controlled. A model predictive current control algorithm is proposed, specifically directed at the utilisation of power obtained from renewable energy systems (RESs). The model was developed for three-phase, multilevel voltage source inverters (MLVSIs), three-phase, three-level diode-clamped converters (DCCs) and flying capacitor converters (FCCs). In this study the renewable energy systems model is used to investigate system performance when power is supplied to a resistiveinductive load (RL-load). The proposed control method was split into two different control algorithms. Firstly, a finite set-model predictive current control (FS-MPCC) method was developed to control the output current of three-phase, MLIs. This control method was selected to reduce the calculation effort for model predictive control (MPC) and to increase the possible prediction horizon. Secondly, to solve the flying capacitor voltage balance problem in an FCC, as well as to solve the DC-link capacitor voltage balance problem in a DCC, a hysteresis-voltage alancing algorithm based on predictive control, was designed—this algorithm was used to keep the flying capacitor voltages and DC-link capacitor voltages within their hysteresis bands. Finally, for some classes of power converters, a performance evaluation of the FS-MPCC method for three-phase, three-level MLIs was investigated in terms of power quality and dynamic response. The improvement was assessed in terms of total harmonic distortion (THD) of the output voltage for the RL-load. The modelling and co-simulation were carried out using MATLAB/Simulink with PSIM software. The co-simulation results indicated that the proposed control algorithms achieved both high performance and a high degree of robustness in RESs applications.

Nowadays, the need for more contributions from renewable energy sources is rapidly growing. This is forced by many factors including the requirements to meet the targeted reductions of greenhouse gas emissions as well as improving the security of energy supply. According to the International Renewable Energy Agency (IRENA) report 2016, the total installed capacity of solar energy was at least 227 GWs worldwide by the end of 2015 with an annual addition of about 50 GWs in 2015, making solar power the world’s fastest growing energy source. The majority of these are grid-connected photo voltaic (PV) solar power plants, which are required be integrated efficiently into the power grids to meet the requirements of power quality standards at the minimum total investment cost. For this, multilevel voltage source inverters (VSI) have been applied extensively in recent years. In practice, there is a trade-off between the inverter’s number of levels and the required size of output filter, which is a key optimisation area. The aim of this research is to propose a generic model to optimise the design number of levels for the Cascaded H-Bridge Multilevel Inverter (CHB-MLI) and the size of output filter for medium voltage – high power applications. The model is based on key measures, including inverter power loss minimisation, efficient control for minimum total harmonic distortion (THD), minimisation of total system cost and proposing the optimum size of output filter. This research has made a contribution to knowledge in the optimisation of CHB-MLI for medium-voltage high-power applications, in particular, the trade-off optimisation of the inverter’s number of levels and the size of the output filter. The main contribution is the establishment and demonstration of a sound methodology and model based on multi-objective optimisation for the considered key measures of the trade-off model. Furthermore, this study has developed a generic precise model for conduction and switching loss calculation in multilevel inverters. Moreover, it applied Genetic Algorithm (GA) optimisation to provide a complete optimum solution for the problem of selective harmonic elimination (SHE) and suggests the optimum size of output passive power filter (PPF) for different levels CHB-MLIs. The proposed trade-off optimisation model presents an efficient tool for finding the optimum number of the inverter’s levels and the size of output filter, in which the integration system is at its lowest cost, based on optimisation dimensions and applied system constraints. The trade-off optimisation model is generic and can be applied to any multilevel inverter topologies and different power applications.

Multilevel voltage source inverters have been receiving more and more attention from the industry and academia as a choice for high voltage and high power applications. The high voltage multilevel inverters can be constructed with existing low voltage semiconductor switches, which already have a mature technology for handling low voltages, thus improving the reliability of the overall inverter system. These multilevel inverters generate the output voltage in the form of multi-stepped waveform with smaller amplitude. This will result in less dv/dt at the motor inputs and electromagnetic interference (EMI) caused by switching is considerably less. Because of the multi-stepped waveform, the instantaneous error in the output voltage will be always less compared to the conventional two-level inverter output voltage. It will reduce the unwanted harmonic content in the output voltage, which will enable to switch the inverter at lower frequencies. Many interesting multi level inverter topologies are proposed by various research groups across the world from industry and academic institutions. But apart from the conventional 3-level NPC and H-bridge topology, others are not yet highly preferred for general high power drives applications. In this respect, two different five-level inverter topologies and one three-level inverter topology for high power induction motor drive applications are proposed in this work. Existing knowledge from published literature shows that, the three-level voltage space vector diagram can be generated for an open-end winding induction motor by feeding the motor phase windings with two two-level inverters from both sides. In such a configuration, each inverter is capable of assuming 8 switching states independent of the other. Therefore a total of 64 switching combinations are possible, whereas the conventional NPC inverter have 27 possible switching combinations. The main drawback for this configuration is that, it requires a harmonic filter or isolated voltage source to suppress the common mode currents through the motor phase winding. In general, the harmonic filters are not desirable because, it is expensive and bulky in nature. Some topologies have been presented, in the past, to suppress the common mode voltage on the motor phase windings when the both inverters are fed with a single voltage source. But these schemes under utilize the dc-link voltage or use the extra power circuit. The scheme presented in chapter-3 eliminates the requirement of harmonic filter or isolated voltage source to block the common mode current in the motor phase windings. Both the two-level inverters, in this scheme, are fed with the same voltage source with a magnitude of Vdc/2 where Vdc is the voltage magnitude requires for the NPC three-level inverter. In this scheme, the identical voltage profile winding coils (pole pair winding coils), in the four pole induction motor, are disconnected electrically and reconnected in two star groups. The isolated neutrals, provided by the two star groups, will not allow the triplen currents to flow in the motor phase windings. To apply identical fundamental voltage on disconnected pole pair winding, decoupled space vector PWM is used. This PWM technique eliminates the first center band harmonics thereby it will allow the inverters to operate at lower switching frequency. This scheme doesn’t require any additional power circuit to block the triplen currents and also it will not underutilize the dc-bus voltage. A five-level inverter topology for four pole induction motor is presented in chapter-3. In this topology, the disconnected pole pair winding coils are effectively utilized to generate a five-level voltage space vector diagram for a four pole induction motor. The disconnected pole pair winding coils are fed from both sides with conventional two-level inverters. Thereby the problems like capacitor voltage balancing issues are completely eliminated. Three isolated voltage sources, with a voltage magnitude of Vdc/4, are used to block the triplen current in the motor phase windings. This scheme is also capable of generating 61 space vector locations similar to conventional NPC five-level inverter. However, this scheme has 1000 switching combinations to realize 61 space vector locations whereas the NPC five-level inverter has 125 switching combinations. In case of any switch failure, using the switching state redundancy, the proposed topology can be operated as a three-level inverter in lower modulation index. But this topology requires six additional bi-directional switches with a maximum voltage blocking capacity of Vdc/8. However, it doesn’t require any complicated control algorithm to generate the gating pulses for bidirectional switches. The above presented two schemes don’t require any special design modification for the induction machine. Although the schemes are presented for four pole induction motor, this technique can be easily extend to the induction motor with more than four poles and thereby the number of voltage levels on the phase winding can be further increased. An alternate five-level inverter topology for an open-end winding induction motor is presented in chapter-4. This topology doesn’t require to disconnect the pole pair winding coils like in the previous propositions. The open-end winding induction motor is fed from one end with a two-level inverter in series with a capacitor fed H-bridge cell, while the other end is connected to a conventional two-level inverter to get a five voltage levels on the motor phase windings. This scheme is also capable of generating a voltage space vector diagram identical to that of a conventional five-level inverter. A total of 2744 switching combinations are possible to generate the 61 space vector locations. With such huge number switching state redundancies, it is possible to balance the H-bridge capacitor voltage for full modulation range. In addition to that, the proposed topology eliminates eighteen clamping diode having different voltage ratings compared to the NPC inverter. The proposed topology can be operated as a three-level inverter for full modulation range, in case of any switch failure in the capacitor fed H-bridge cell. All the proposed topologies are experimentally verified on a 5 h.p. four pole induction motor using V/f control. The PWM signals for the inverters are generated using the TMS320F2812 and GAL22V10B/SPARTAN XC3S200 FPGA platforms. Though the proposed inverter topologies are suggested for high-voltage and high-power industrial IM drive applications, due to laboratory constraints the experimental results are taken on the 5h.p prototypes. But all the proposed schemes are general in nature and can be easily implemented for high-voltage high-power drive applications with appropriate device ratings.

In the past two decades the core aircraft technology is going through a drastic change. The traditional technologies that is almost half a century old, is going through a complete revamp. In the new “More Electric Aircraft” technology many mechanical, pneumatic and hydraulic systems are being replaced by electrical and power electronic systems. Airbus-A380, Boeing B-787 are the pioneers in the family of these new breed of aircrafts. As the aircraft technology is moving towards “More Electric”, more and more electric motors and motor controllers are being used in new aircrafts. Number of electric motor drive systems has increased by about ten times in more electric aircrafts compared to traditional aircrafts. Weight of any electric component that goes into aircraft needs to be low to reduce the overall weight of aircraft so as to improve the fuel efficiency of the aircraft. Hence there is an increased need to reduce weight of motors and motor controllers in commercial aircraft. High speed ironless axial flux permanent magnet brushless dc motors are becoming popular in the new more-electric aircrafts because of their ability to meet the demand of light weight, high power density, high efficiency and high reliability. However, these motors come with very low inductance, which poses a big challenge to the motor controllers in controlling the ripple current in motor windings. Multilevel inverters can solve this problem. Three-level inverters are proposed in this thesis for driving axial flux BLDC motors in aircraft. Majority of the motors in new more electric aircrafts are in the power range of 2kW to 20kW, while a few motor applications being in the range of 100kW to 150kW. Motor controllers in these applications run from 270Vdc or 540Vdc bus which is the standard in new more electric aircraft architecture. Multilevel Inverter is popular in the industry for high power and high voltage applications, where high-voltage power switching devices like IGBT, GTO are popularly used. However multilevel inverters have not been tried in the low power range which is appropriate for aircraft applications. A detail analysis of practical feasibility of constructing three-level inverter in lower power and voltage level is presented in this thesis. Analysis is presented that verify the advantages of driving low voltage and low power (300Vdc to 600Vdc and less than 100kW) motors with multilevel inverters. Practical considerations for design of MOSFET based three-level inverter are investigated and topological modifications are suggested. The effect of clamping diodes in the diode clamped multilevel inverters play an important role in determining its efficiency. SiC diodes are proposed to be used as clamping diodes. Further, it is realised that power loss introduced by reverse recovery of MOSFET body diode prohibits use of MOSFET in hard switched inverter legs. Hence, a technique of avoiding the reverse recovery losses of MOSFET body diode in three-level NPC inverter is conceived. The use of proposed multilevel inverter topology enables operation at high switching frequency without sacrificing efficiency. High switching frequency of operation reduces the output filter requirement, which in turn helps reducing size of the inverter. In this research work elaborate trade-off analysis is done to quantify the suitability of multilevel inverters in the low power applications. For successful operation of three-level NPC inverter in aircraft electrical system, it is important for the DC bus structure in aircraft electric primary distribution system to be compatible to drive NPC inverters. Hence a detail study of AC to DC power conversion system as applied to commercial aircraft electrical system is done. Multi-pulse rectifiers using autotransformers are used in aircrafts. Investigation is done to improve these rectifiers for future aircrafts, such that they can support new technologies of future generation motor controllers. A new 24-pulse isolated transformer rectifier topology is proposed. From two 15º displaced 6-phase systems feeding two 12-pulse rectifiers that are series connected, a 24-pulse rectifier topology is obtained. Though, windings of each 12-pulse rectifiers are isolated from primary, the 6-phase generation is done without any isolation of the transformer windings. The new 24-pulse transformer topology has lower VA rating compared to standard 12-pulse rectifiers. Though the new 24-pulse transformer-rectifier solution is robust and simple, it adds to the weight of the overall system, as compared to the present architecture as the proposed topology uses isolated transformer. Non-isolated autotransformer cannot provide split voltage at the dc-link that creates a stable mid-point voltage as required by the three-level NPC inverter. Hence, a new front-end AC-DC power conversion system with switched capacitor is conceived that can support motor controllers driven by three-level inverters. Laboratory experimental results are presented to validate the new proposed topology. In this proposed topology, the inverter dc-link voltage is double the input dc-link voltage. An intense research work is performed to understand the operation of Trapezoidal Back EMF BLDC motor driven by three-Level NPC inverter. Operation of BLDC motor from three-Level inverter is primarily advantageous for low inductance motors, like ironless axial flux motors. For low inductance BLDC motor, very high switching frequency is required to limit the magnitude of ripple current in motor winding. Three-level inverters help limiting the magnitude of motor ripple current without increasing the switching frequency to very high value. Further, it is analysed that dc link mid-point current in three-level NPC inverter for driving trapezoidal BLDC motor has a zero average current with fundamental frequency same as switching frequency. Because of this, trapezoidal BLDC motors can easily be operated from three-level NPC inverter without any special attention given to mid-point voltage unbalance. One non-ideal condition arrives in practical implementation of the inverter that leads to non-zero average mid point current. Unequal gate drive dead time delays from one leg to other leg of inverter introduce dc-link mid-point voltage unbalance. For the motoring mode operation of trapezoidal BLDC motor drive, simple gate drive logic is researched that eliminates need of the gate drive dead-time, and hence solves the mid-point voltage unbalance issue. Simple closed loop control scheme for mid-point voltage balancing also is also proposed. This control scheme may be used in applications where very precise control of speed and torque ripple is warranted. All the investigations reported in this thesis are simulated extensively on MATHCAD and MATLAB platform using SIMULINK toolbox. A laboratory experimental set-up of three-Level inverter driving axial flux BLDC motor is built. The three-level inverter, operating from 300Vdc bus is built using 500V MOSFETs and 600V SiC diodes. All the control schemes are implemented digitally on digital signal processor TMS320F2812 DSP platform and GAL22V10B platforms. Experimental results are collected to validate the theoretical propositions made in the present research work. At the end, in chapter 5, some future works are proposed. A new external voltage balance circuit is proposed where the inverter dc-link voltage is same as the input dc-link voltage. This topology is based on the resonant converter principle and uses a lighter resonant inductor than prior arts available in literature. Detail simulation and experimentation of this topology may be carried out to validate the industrial benefits of this circuit. It is also thought that current source inverters may work as an alternative to voltage source inverters for driving BLDC motors. Current source inverters eliminate use of bulky DC-link capacitors. Long term reliability of current source inverters is higher than voltage source inverters due to the absence of possibility of shoot-through. Further, in voltage source inverters, the voltage at the motor terminal is limited by the source voltage (dc-link voltage). This issue is eliminated in current source inverters. An interface circuit is conceived to reduce the size of dc-link inductors in current source inverters, pending detail analysis and experimental verification. The interface circuit bases its fundamentals on the principles of operation of multilevel inverters for BLDC motors that is presented in this thesis.

Multilevel inverters are very popular for medium and high-voltage induction motor (IM) drive applications. They have superior performance compared to 2-level inverters such as reduced harmonic content in output voltage and current, lower common mode voltage and dv/dt, and lesser voltage stress on power switches. To get nearly sinusoidal current waveforms, the switching frequency of the conventional inverters have to be in¬creased. This will lead to higher switching losses and electromagnetic interference. The problem in using lower switching frequency is the introduction of low order harmonics in phase currents and undesirable torque ripple in the motor. The 5th and 7th harmonics are dominant for hexagonal voltage space-vector based low frequency switching. Dodecagonal voltage space-vector based multilevel inverters have been proposed as an improvement over the conventional hexagonal space vector based inverters. They achieve complete elimination of 5th and 7th order harmonics throughout the modulation range. The linear modulation range is also extended by about 6.6%, since the dodecagon is closer to circle than a hexagon. The previous works on dodecagonal voltage space vector based VSI fed drives used voltage controlled PWM (VC-PWM). Although these controllers are more popular, they have inferior dynamic performance when compared to current controlled PWM (CC¬PWM). VSIs using current controlled PWM have excellent dynamic response, inherent short-circuit protection and are simple to implement. The conventional CC-PWM tech¬niques have large switching frequency variation and large current ripple in steady-state. xix As a result, there has been significant research interest to achieve current controlled VSI fed IM drives with constant switching frequency. Two current error space vector (CESV) based hysteresis controllers for dodecagonal voltage space-vector based VSI fed induction motor drives are proposed in this work. The proposed controllers achieve nearly constant switching frequency at steady state operation, similar to VC-SVPWM based VSI fed IM drives. They also have fast dynamic response while at the same time achieving complete elimination of fifth and seventh order harmonics for the entire modulation range, due to dodecagonal voltage vector switching. The first work proposes a nearly constant switching frequency current error space vector (CESV) based hysteresis controller for an IM drive with single dodecagonal voltage space vectors. Parabolic boundaries computed offline are used in the proposed controller. An open-end winding induction motor is fed from two inverters with asymmetrical DC link voltages, to generate the dodecagonal voltage space vectors. The drive scheme is first studied at different frequencies with a space vector based PWM (SVPWM) control, to obtain the current error space vector boundaries. The CESV boundary at each frequency can be approximated with four parabolas. These parabolic boundaries are used in the proposed controller to limit the CESV trajectory. Due to symmetries in the parabolas only two set of parabola parameters, at different frequencies, need to be stored. A generalized next vector selection logic, valid for all sectors and rotation direction, is used in the proposed controller. For this an axis transformation is done in all sectors, to bring the CESV trajectory to the first sector. The sector information is obtained from the estimated fundamental stator phase voltage. The proposed controller is extensively studied using vector control at different frequencies and transient conditions. This controller maintains nearly constant switching frequency at steady state operation, similar to VC-SVPWM inverters, while at the same time achieving better dynamic performance and complete elimination of 5th and 7th order harmonics throughout the modulation range. In the second work the nearly constant switching frequency current hysteresis con¬troller is extended to multilevel dodecagonal voltage space-vector based IM drives, with online computation of CESV boundaries. The multilevel dodecagonal space-vector dia¬gram has different types of triangles, and the previously proposed methods for multilevel hexagonal VSI based current hysteresis controllers cannot be used directly. The CESV trajectory of the VC-SVPWM, obtained for present triangular region, is used as the reference trajectory of the proposed controller. The CESV reference boundaries are com¬puted online, using switching dwell time and voltage error vector of each applied vector. These quantities are calculated from estimated sampled reference phase voltages, which are found out from the stator current error ripple and the parameters of the induction motor. Whenever the actual current error space vector crosses the reference CESV tra¬jectory, an appropriate vector that will force it along the reference trajectory is switched. Extensive study of the proposed controller using vector control is done at different fre¬quencies and transient conditions. This controller has all the advantages of multilevel switching like low dv/dt, lesser electromagnetic interference, lower switch voltage stress and lesser harmonic distortion, in addition to all the dynamic performance advantages of the previous controller. The third work proposes an elegant 5th and 7th order harmonic suppression tech¬nique for open end winding split-phase induction motors, using capacitor fed inverters. Split-phase induction motors have been proposed to reduce the torque and flux ripples of conventional three-phase IM. But these motors have high 5th and 7th order harmonics in the stator windings due to lack of back-emf for these frequencies. A space-vector harmonic analysis of the split-phase IM is conducted and possible 5th and 7th order harmonic sup¬pression techniques studied. A simple harmonic suppression scheme is proposed, which requires the use of only capacitor fed inverters. A PWM scheme that can maintain the capacitor voltage as well as suppress the 5th and 7th order harmonics is also proposed. To test the performance of the proposed scheme, an open-loop v/f control is used on an open-end winding split-phase induction motor under no-load condition. Synchronized PWM with two samples per sector was used, for frequencies above 10 Hz. The har¬monic spectra of the phase voltages and currents were computed and compared with the traditional SVPWM scheme, to highlight the harmonic suppression. The concepts were initially simulated in Matlab/Simulink. Experimental verifica¬tion was done using laboratory prototypes at low power. While these concepts maybe easily extended to higher power levels by using suitably rated devices, the control tech¬niques presented shall still remain applicable. TMS320F2812 DSP platform was used to execute the control code for the proposed drive schemes. For the first work the output pins of the DSP was directly used to drive the inverter switches through a dead-band circuit. For the other two works, DSP outputs the sector information and the PWM signals. The PWM terminals and I/O lines of the DSP is used to output the timings and the triangle number respectively. An FPGA (XC3S200) was used to translate the sector information and the PWM signals to IGBT gate signal logic. A constant dead-time of 1.5 µs was also implemented inside the FPGA. Opto-isolated gate drivers with desaturation protection (M57962L) were used to drive the IGBTs. The phase currents and DC bus voltages were measured using hall-effect sensors. An incremental shaft position encoder was also connected to the motor to measure the angular velocity. The switches were realized using 1200 V, 75 A IGBT half bridge modules.