No description available.

No description available.

This paper designs and implements a DSP-microprocessor based variable frequency motor drive. We control the induction motor with V/F scheme. This paper also analysis about Sine-PWM and Space-Vector-PWM. Compared with commonly used SPWM method, SVPWM has the advantages of higher voltage utilization, lower harmonic and lower switching loss. Also, it increases the efficiency of an inverter. To calculate duty cycle this paper support different update model, so symmetrical and asymmetrical PWM are generated. To analyse about spectra, and we can find the asymmetrical PWM restrain the harmonic.

Abstract: This paper designs and implements a DSP-microprocessor based motor driver. We control the induction motor with V/F scheme. And we module all circuits with PCB Layout.This Inverter is compose of digital board and analog-power board. We connect two parts, and we use a three phase induction motorto to be the load. Because the digital board is compose of DSP, it is to fit a lot of mathematics. It is easy to use the software to present the theory. So the paper compute the three phase gate signals with asymmetrical Pulse-Width-Modulation model.

The thesis will be established as digital Inverter with analog power board and DSP kernel. We can accomplish effective ac motor control with VVVF mode by powerful arithmetic ability of DSP. Furthermore, we can obtain rotor speed by calculating the feedback voltage and current of motor from sensors. We adopt the new integrator scheme to replace traditional pure integrator to solve the dc drift and initial value problems. Meanwhile, we can compensate the voltage distortion caused by dead time to decrease current ripple via judging the direction of current. Because we have modulized our circuits, it is very convenient that we can achieve modern control theories by software modification only.

In vector control of induction motors it is essential to know the parameters of the motor. Known approaches to this problem have some drawbacks. This thesis work is planned to develop solutions to the existing problems. The proposed solutions will be implemented and tested.

High dynamic performance, which is obtained from dc motors, became achievable from induction motors with the recent advances in power semiconductors, digital signal processors and development in control techniques. By using field oriented control, torque and flux of the induction motors can be controlled independently as in dc motors. The control performance of field oriented induction motor drive greatly depends on the correct stator flux estimation. In this thesis voltage model is used for the flux estimation. Stator winding resistance is used in the voltage model. Also leakage inductance, mutual inductance and referred rotor resistance values are used in vector control calculations. Motor control algorithms use motor models, which depend on motor parameters, so motor parameters should be measured accurately. Induction motor parameters may be measured by conventional no load and locked rotor test. However, an intelligent induction motor drive should be capable of identifying motor parameters itself. In this study parameter estimation algorithms are implemented and motor parameters are calculated. Then these parameters are used and rotor flux oriented vector control is implemented. Test results are presented.

This thesis presents different state estimation techniques for speed sensorlees field oriented control of induction motors. The theoretical basis of each algorithm is explained in detail and its performance is tested with simulations and experiments individually. First, a stochastical nonlinear state estimator, Extended Kalman Filter (EKF) is presented. The motor model designed for EKF application involves rotor speed, dq-axis rotor fluxes and dq-axis stator currents. Thus, using this observer the rotor speed and rotor fluxes are estimated simultaneously. Different from the widely accepted use of EKF, in which it is optimized for either steady-state or transient operations, here using adjustable noise level process algorithm the optimization of EKF has been done for both states / the steady-state and the transient-state of operations. Additionally, the measurement noise immunity of EKF is also investigated. Second, Unscented Kalman Filter (UKF), which is an updated version of EKF, is proposed as a state estimator for speed sensorless field oriented control of induction motors. UKF state update computations, different from EKF, are derivative free and they do not involve costly calculation of Jacobian matrices. Moreover, variance of each state is not assumed Gaussian, therefore a more realistic approach is provided by UKF. In this work, the superiority of UKF is shown in the state estimation of induction motor. Third, Model Reference Adaptive System is studied as a state estimator. Two different methods, back emf scheme and reactive power scheme, are applied to MRAS algorithm to estimate rotor speed. Finally, a flux estimator and an open-loop speed estimator combination is employed to observe stator-rotor fluxes, rotor-flux angle and rotor speed. In flux estimator, voltage model is assisted by current model via a closed-loop to compensate voltage model&rsquo / s disadvantages.

Multi-level inverters play a significant role in high power drive systems for induction motors. Interest in multi-level inverters started with the three-level, neutral point clamped (NPC) inverter. Now there are many topologies for higher number of levels such as the, flying capacitor and cascaded H-bridge etc. The advantage of multi-level inverters is the reduced voltage stress on the switching devices, lower dv/dt and lower harmonic content. The voltage space vector structure in a multi-level inverter has a hexagonal periphery similar to that in a two-level inverter. In the over-modulation region in multi-level inverters, there is the presence of lower order harmonics such as 5th and 7th in the output voltage, and this can be avoided by using a voltage space vector scheme with more than six polygonal voltage space vectors such as 12, 18, 24 etc. These polygonal voltage space vectors can be generated by using multi-level inverter topologies, by cascading two-level inverter structures with asymmetric DC-links. This thesis deals with the development of 12-sided and 18-sided polygonal voltage space vector schemes for induction motor drives. With the 12-sided polygonal structure, all the 5th and 7th harmonic orders and 6n±1, n=1, 3, 5.. are absent throughout the modulation range, and in the 18-sided voltage space vector scheme, 5th, 7th, 11th and 13th harmonics are absent throughout the modulation range. With the absence of the low order frequencies in the proposed polygonal space vector structures, high frequency PWM schemes are not needed for voltage control. This is an advantage over conventional schemes. Also, due to the absence of lower order harmonics throughout the modulation range, special compensated synchronous reference frame PI controllers are not needed in current controlled vector control schemes in over-modulation. In this thesis a method is proposed for generating 12-sided polygonal voltage space vectors for an induction motor fed from one side. A cascaded combination of three two-level inverters is used with asymmetrical DC-links. A simple space vector PWM scheme based only on the sampled reference phase amplitudes are used for the inverter output voltage control. The reference space vector is sampled at different sampling rates depending on the frequency of operation. The number of samples in a sector is chosen to keep the overall switching frequency around 1kHz, in order to minimize switching losses. The voltage space vectors that make up the two sides of the sector in which the reference vector lies, are time averaged using volt-sec balance, to result in the reference vector. In the proposed 12-sided PWM scheme all the harmonics of the order 6n±1, n=1, 3, 5... are eliminated from the phase voltage, throughout the modulation range. In multi-level inverters steps are taken to eliminate common-mode voltage. Common-mode voltage is defined as one third of the sum of the three pole voltages of the inverter for a three phase system. Bearings are found to fail prematurely in drives with fast rising voltage pulses and high frequency switching. The alternating common-mode voltage generated by the PWM inverter contributes to capacitive couplings from stator body to rotor body. This generates motor shaft voltages causing bearing currents to flow from rotor to stator body and then to the ground. There can be a flashover between the bearing races. Also a phenomenon termed EDM (Electro-discharge machining) effect occurs and may damage the bearings. Common-mode voltage has to be eliminated in order to overcome these effects. In multi-level inverters redundancy of space vector locations is used to eliminate common-mode voltages. In the present thesis a 12-sided polygonal voltage space vector based inverter with an open-end winding induction motor is proposed, in which the common-mode voltage variation at the poles of the inverter is eliminated. In this scheme, there is a three-level inverter on each side of the open-end winding of the induction motor. The three-level inverter is made by cascading two, two-level inverters with unequal DC-link voltages. Appropriate space vectors are selected from opposite sides such that the sum of the pole voltages on each side is a constant. Also during the PWM operation when the zero vector is applied, identical voltage levels are used on both sides of the open-end windings, in order to make the phase voltages zero, while the common-mode voltage is kept constant. This way, common-mode voltage variations are eliminated throughout the modulation range by appropriately selecting the voltage vectors from opposite ends. In this method all the harmonics of 6n±1, n=1, 3, 5.. and triplen orders are eliminated. In the 12-sided polygonal voltage space vector methods, the 11th and 13th harmonics though attenuated are not eliminated. In the 18-sided polygonal voltage space vector method the 11th and 13th harmonics are eliminated along with the 5th and 7th harmonics. This scheme consists of an open-end winding induction motor fed from one side by a two-level inverter and the other side by a three-level inverter comprising of two cascaded two-level inverters. Asymmetric DC-links of a particular ratio are present. The 12-sided and 18-sided polygonal voltage space vector methods have been first simulated using SIMULINK and then verified experimentally on a 1.5kW induction motor drive. In the simulation as well as the experimental setup the starting point is the generation of the three reference voltages v, vB and vC . A method for determining the sector in which the reference vector lies by comparing the values of the scaled sampled instantaneous reference voltages is proposed. For the reference vector lying in a sector between the two active vectors, the first vector is to be kept on for T1 duration and the second vector for T2 duration. These timing durations can be found from the derived formula, using the sampled instantaneous values of the reference voltages and the sector information. From the pulse widths and the sector number, the voltage level at which a phase in the inverter has to be maintained is uniquely determined from look-up tables. Thus, once the pole voltages are determined the phase voltages can be easily determined for simulation studies. By using a suitable induction motor model in the simulation, the effect of the PWM scheme on the motor current can be easily obtained. The simulation studies are experimentally verified on a 1.5kW open-end winding induction motor drive. A V/f control scheme is used for the study of the drive scheme for different speeds of operation. A DSP (TMS320LF2407A) is used for generating the PWM signals for variable speed operation. The 12-sided polygonal voltage space vector scheme with the motor fed from a single side has a simple power bus structure and it is also observed that the pole voltage is clamped to zero for 30% of the time duration of one cycle of operation. This will increase the overall efficiency. The proposed scheme eliminates all harmonics of the order 6n±1, n=1, 3, 5…for the complete modulation range. The 12-sided polygonal voltage space vector scheme with common-mode elimination requires the open-end winding configuration of the induction motor. Two asymmetrical DC-links are required which are common to both sides. The leg of the high voltage inverter is seen to be switched only for 50% duration in a cycle of operation. This will also reduce switching losses considerably. The proposed scheme not only eliminates all harmonics of the order 6n±1, n=1, 3, 5…for the complete modulation range, but also maintains the common-mode voltage on both sides constant. The common-mode voltage variation is eliminated. This eliminates bearing currents and shaft voltages which can damage the motor bearings. In the 18-sided polygonal voltage space vector based inverter, the 11th and 13th harmonics are eliminated along with the 5th and 7th. Here also an open-end winding induction motor is used, with a two-level inverter on one side and a three-level inverter on the other side. A pole of the two-level inverter is at clamped to zero voltage for 50% of the time and a pole of the three-level inverter is clamped to zero for 30% of the time for one cycle of operation. The 18-sided polygonal voltage space vectors show the highest maximum peak fundamental voltage in the 18-step mode of 0.663Vdc compared to 0.658Vdc in the 12-step mode of the 12-sided polygonal voltage space vector scheme and 0.637Vdc in the six-step mode of a two-level inverter or conventional multi-level inverter (where Vdc is the radius of the space vector polygon). Though the schemes proposed are verified on a low power laboratory prototype, the principle and the control algorithm development are general in nature and can be easily extended to induction motor drives for high power applications.

Multilevel inverters have advantages over two-level inverters such as reduced THD, ability to operate at low switching frequencies, reduced switching losses etc. Moreover, higher voltage levels can be handled with devices of lower voltage rating. The main disadvantage with the multilevel configurations compared to the two-level inverter configuration is the increase in the number of power devices required and the circuit complexity, which necessitates complex control schemes that add to the cost. Also, the reliability of the converters comes down as the number of devices increases. Reduction in complexity and modularity are desirable characteristics for the multilevel inverters. Open-end winding Induction Motor (IM) drive configurations are shown to have advantages over the motor drive schemes with isolated neutral. The DC-link requirement in case of open-end winding structures comes down to half the voltage rating of the conventional NPC inverters. The DC- link requirement in case of open-end winding structures comes down to half compared to that of the conventional NPC inverters. The number of switching states is higher in the case of open-end winding configuration compared to multiplicity of switching states of conventional NPC inverters, which gives a control flexibility that can be used for optimizing the hardware requirements. Taking advantage of the flexibility given by open-end winding configuration, this thesis proposes schemes which have reduced power circuit complexity. Non-sinusoidal voltage fed IM drives suffer from the problems related to the common mode voltage (CMV) generated by the inverters. This CMV causes bearing currents and shaft voltages which in turn cause increased conducted EMI, ground loop currents and premature bearing failure. A three-level scheme was proposed for an open-end winding Induction machine in the literature, which completely eliminate the CMV variation from the pole voltages as well as the phase voltages. This configuration uses 24 controlled switches and two isolated DC-sources. In this thesis, three-level inverter schemes with CMV elimination and reduced power device count for an open-end winding IM drive are proposed. The first scheme gets the reduction in switch count by sharing the top inverter of the three-level scheme and the second scheme achieves the same by sharing the bottom inverter. This way, the number of controlled switches comes down to 18 from 24. Another problem with multilevel inverters is the large number of isolated DC-sources required to achieve the multilevel inversion. Reducing the number of isolated supplies and using capacitors to split the voltage levels poses the problem of capacitor voltage balancing. A four-level inverter with both CMV elimination and capacitor voltage balancing for an open-end winding IM drive is proposed in this thesis. The motor is fed by two four-level inverters from both the sides. A closed loop capacitor voltage balancing scheme is implemented and the redundancies in the switching states are used for achieving the capacitor voltage balancing and thereby reducing the total number of DC-link to two. The control scheme is independent of the load power factor and maintains the balance in the entire modulation range. A five-level inverter scheme is proposed for an open-end winding IM drive in this thesis. It requires only two isolated DC-sources to achieve the five-level inversion. The motor is fed by one NPC three-level inverter from one side and a two-level inverter from the other. The inverters on either side share the DC-sources. Common mode voltage in the phases are made zero in an average sense using sine-triangle modulation in the proposed scheme so that the common mode currents through the phases are suppressed. The maximum fundamental voltage that can be obtained at the phase is limited to 0.5Vdc. DC-link requirement of the inverter scheme is half of that of conventional five-level inverter scheme because of the open-end winding structure. The two-level inverter, which should withstand half the DC-link voltage, is always in square wave operation and hence the switching losses are very less. All the schemes are simulated extensively in MATLAB/Simulink and experimentally verified on laboratory prototypes under V/f control. TI Motor control DSP and Xilinx CPLD/FPGA are used for generation of the PWM signals for the schemes. The inverters are switched at around 1.25 kHz to keep the switching losses low. Due to laboratory constraints, the experimental verification is done on low power prototypes. Nonetheless, the generality of the schemes allow them to be used for medium voltage high power applications.