In Part I, the design of an ASIC control chip for a forward active clamp converter is presented. Integration of the control and drive circuit into one IC chip results in higher power density, higher reliability for the converter module. The designed ASIC control chip uses a 2.0 um N well Analog CMOS process, and is fabricated at MOSIS. The design procedures of the ASIC chip are explained, and experimental results are presented. Part II of the thesis focuses on the numerical investigation of several integratable lateral power devices. Lateral power devices are used in power IC designs because of their compatibility with analog & digital IC process. To obtain devices with high current density, large safe operating area, fast response and low cost is highly desirable for power ICs. In Part II of this thesis, several lateral power devices are discussed and simulated, including lateral IGBT, lateral MCT and double gate lateral MCTs. It is shown that lateral IGBT and lateral MCTs are good candidates for power IC applications. / Master of Science

Multi-level inverters play a significant role in high power drive systems for induction motors. Interest in multi-level inverters started with the three-level, neutral point clamped (NPC) inverter. Now there are many topologies for higher number of levels such as the, flying capacitor and cascaded H-bridge etc. The advantage of multi-level inverters is the reduced voltage stress on the switching devices, lower dv/dt and lower harmonic content. The voltage space vector structure in a multi-level inverter has a hexagonal periphery similar to that in a two-level inverter. In the over-modulation region in multi-level inverters, there is the presence of lower order harmonics such as 5th and 7th in the output voltage, and this can be avoided by using a voltage space vector scheme with more than six polygonal voltage space vectors such as 12, 18, 24 etc. These polygonal voltage space vectors can be generated by using multi-level inverter topologies, by cascading two-level inverter structures with asymmetric DC-links. This thesis deals with the development of 12-sided and 18-sided polygonal voltage space vector schemes for induction motor drives. With the 12-sided polygonal structure, all the 5th and 7th harmonic orders and 6n±1, n=1, 3, 5.. are absent throughout the modulation range, and in the 18-sided voltage space vector scheme, 5th, 7th, 11th and 13th harmonics are absent throughout the modulation range. With the absence of the low order frequencies in the proposed polygonal space vector structures, high frequency PWM schemes are not needed for voltage control. This is an advantage over conventional schemes. Also, due to the absence of lower order harmonics throughout the modulation range, special compensated synchronous reference frame PI controllers are not needed in current controlled vector control schemes in over-modulation. In this thesis a method is proposed for generating 12-sided polygonal voltage space vectors for an induction motor fed from one side. A cascaded combination of three two-level inverters is used with asymmetrical DC-links. A simple space vector PWM scheme based only on the sampled reference phase amplitudes are used for the inverter output voltage control. The reference space vector is sampled at different sampling rates depending on the frequency of operation. The number of samples in a sector is chosen to keep the overall switching frequency around 1kHz, in order to minimize switching losses. The voltage space vectors that make up the two sides of the sector in which the reference vector lies, are time averaged using volt-sec balance, to result in the reference vector. In the proposed 12-sided PWM scheme all the harmonics of the order 6n±1, n=1, 3, 5... are eliminated from the phase voltage, throughout the modulation range. In multi-level inverters steps are taken to eliminate common-mode voltage. Common-mode voltage is defined as one third of the sum of the three pole voltages of the inverter for a three phase system. Bearings are found to fail prematurely in drives with fast rising voltage pulses and high frequency switching. The alternating common-mode voltage generated by the PWM inverter contributes to capacitive couplings from stator body to rotor body. This generates motor shaft voltages causing bearing currents to flow from rotor to stator body and then to the ground. There can be a flashover between the bearing races. Also a phenomenon termed EDM (Electro-discharge machining) effect occurs and may damage the bearings. Common-mode voltage has to be eliminated in order to overcome these effects. In multi-level inverters redundancy of space vector locations is used to eliminate common-mode voltages. In the present thesis a 12-sided polygonal voltage space vector based inverter with an open-end winding induction motor is proposed, in which the common-mode voltage variation at the poles of the inverter is eliminated. In this scheme, there is a three-level inverter on each side of the open-end winding of the induction motor. The three-level inverter is made by cascading two, two-level inverters with unequal DC-link voltages. Appropriate space vectors are selected from opposite sides such that the sum of the pole voltages on each side is a constant. Also during the PWM operation when the zero vector is applied, identical voltage levels are used on both sides of the open-end windings, in order to make the phase voltages zero, while the common-mode voltage is kept constant. This way, common-mode voltage variations are eliminated throughout the modulation range by appropriately selecting the voltage vectors from opposite ends. In this method all the harmonics of 6n±1, n=1, 3, 5.. and triplen orders are eliminated. In the 12-sided polygonal voltage space vector methods, the 11th and 13th harmonics though attenuated are not eliminated. In the 18-sided polygonal voltage space vector method the 11th and 13th harmonics are eliminated along with the 5th and 7th harmonics. This scheme consists of an open-end winding induction motor fed from one side by a two-level inverter and the other side by a three-level inverter comprising of two cascaded two-level inverters. Asymmetric DC-links of a particular ratio are present. The 12-sided and 18-sided polygonal voltage space vector methods have been first simulated using SIMULINK and then verified experimentally on a 1.5kW induction motor drive. In the simulation as well as the experimental setup the starting point is the generation of the three reference voltages v, vB and vC . A method for determining the sector in which the reference vector lies by comparing the values of the scaled sampled instantaneous reference voltages is proposed. For the reference vector lying in a sector between the two active vectors, the first vector is to be kept on for T1 duration and the second vector for T2 duration. These timing durations can be found from the derived formula, using the sampled instantaneous values of the reference voltages and the sector information. From the pulse widths and the sector number, the voltage level at which a phase in the inverter has to be maintained is uniquely determined from look-up tables. Thus, once the pole voltages are determined the phase voltages can be easily determined for simulation studies. By using a suitable induction motor model in the simulation, the effect of the PWM scheme on the motor current can be easily obtained. The simulation studies are experimentally verified on a 1.5kW open-end winding induction motor drive. A V/f control scheme is used for the study of the drive scheme for different speeds of operation. A DSP (TMS320LF2407A) is used for generating the PWM signals for variable speed operation. The 12-sided polygonal voltage space vector scheme with the motor fed from a single side has a simple power bus structure and it is also observed that the pole voltage is clamped to zero for 30% of the time duration of one cycle of operation. This will increase the overall efficiency. The proposed scheme eliminates all harmonics of the order 6n±1, n=1, 3, 5…for the complete modulation range. The 12-sided polygonal voltage space vector scheme with common-mode elimination requires the open-end winding configuration of the induction motor. Two asymmetrical DC-links are required which are common to both sides. The leg of the high voltage inverter is seen to be switched only for 50% duration in a cycle of operation. This will also reduce switching losses considerably. The proposed scheme not only eliminates all harmonics of the order 6n±1, n=1, 3, 5…for the complete modulation range, but also maintains the common-mode voltage on both sides constant. The common-mode voltage variation is eliminated. This eliminates bearing currents and shaft voltages which can damage the motor bearings. In the 18-sided polygonal voltage space vector based inverter, the 11th and 13th harmonics are eliminated along with the 5th and 7th. Here also an open-end winding induction motor is used, with a two-level inverter on one side and a three-level inverter on the other side. A pole of the two-level inverter is at clamped to zero voltage for 50% of the time and a pole of the three-level inverter is clamped to zero for 30% of the time for one cycle of operation. The 18-sided polygonal voltage space vectors show the highest maximum peak fundamental voltage in the 18-step mode of 0.663Vdc compared to 0.658Vdc in the 12-step mode of the 12-sided polygonal voltage space vector scheme and 0.637Vdc in the six-step mode of a two-level inverter or conventional multi-level inverter (where Vdc is the radius of the space vector polygon). Though the schemes proposed are verified on a low power laboratory prototype, the principle and the control algorithm development are general in nature and can be easily extended to induction motor drives for high power applications.

This work deals with the usage of magneto-rheological (MR) damper in the semi-active car suspension. Semi-active suspension can improve ride comfort or tyre grip to the level, which cannot be achieved with the common passive setting of the damper. MR damper has however features, like time response of the controller with MR damper and the control range of the MR damper, which limit area of application. It was found out that especially the time response of the damper significantly influences the efficiency of semi-active algorithms. Current MR dampers with controllers are not capable of efficient control of the semi-active suspension. For proper design of semi-active suspension with MR dampers, the time response must be decreased. Therefore, a new PWM current controller was designed and verified. Also changes in MR damper design which eliminate eddy-currents in the magnetic circuit were proposed. The results of this work should contribute to the better design of semi-active suspension systems with MR damper.

Digitally controlled switching DC-DC converters have recently emerged as an attractive alternative to conventional switching converters based on analog control techniques. This research focuses on eliminating the issues associated with the state of the art switching converters by proposing three novel control techniques: (1) a digitally controlled Buck-Boost converter uses a fully synthesized constant ON/OFF time-based fractional-N controller to regulate the output over a 3.3V-to-5.5V input voltage range and provides seamless transition from buck to buck-boost modes (2) a hysteretic buck converter that employs a highly digital hybrid voltage/current mode control to regulate output voltage and switching frequency independently (3) a 10MHz continuous time PID controller using time based signal processing which alleviates the speed limitations associated with conventional analog and digital. All the three techniques employ digitally assisted control techniques and require no external compensation thus making the controllers fully integrated and highly cost effective. / Graduation date: 2013 / Access restricted to the OSU Community at author's request from June 25, 2012 - June 25, 2014

This master thesis is focused on proposition and following implementation of DC arc welder. This paper is based on semester’s paper, where the first version was realized. The welder is powered by a battery pack with LiFePO4 type cells. Battery cells are protected by BMS circuits. The driving electronics controls the duty cycle step-down (buck) converter in a closed current or power regulation loop. The power regulator has been designed and validated by simulations. Switching power transistors, low side and high side, are implemented by optically isolated gate drivers. Charging the battery is solved by a switching flyback converter. For the charger and the welder is sheet metal construction made of aluminum sheet.