CoordenaÃÃo de AperfeiÃoamento de Pessoal de NÃvel Superior / This work presents a comparative evaluation of three single-phase neutral point clamped multilevel inverters, based on switching cells, which have as a common characteristic the capacity increase of the total output current of the converters without increasing the current efforts in semiconductors. The technique employed to perform this evaluation consists primarily on individual analysis of the classical three level topology, applying only the parallelism of switching cells. Then a detailed analysis of the main topology evaluated in this work is performed. It is the five level neutral point clamped inverter, based on multi-state switching cell, which uses multilevel interleaved converters, coupled magnetically through an autotransformer in order to distribute uniformly the total output current between their windings, and consequently between the semiconductors of the converter. In addition to presenting reduced conduction losses in the semiconductors, this technique also provides a reduction in volume and weight of magnetic components due to frequency of operation of reactive elements is a multiple of the switching frequency of the switches. Consequently, the resulting converters present high efficiency, high power density and low harmonic distortion for the output voltage and output current. The theoretical analysis of the five level neutral point clamped inverter, based on multi-state switching cell, is verified by digital simulation and by 5 kW prototypes experimentation. Simulation and experimental results are also presented for the third topology analyzed, the five level neutral point clamped inverter, based on interleaved switching cells. Finally, a comparative evaluation is performed for the three inverters analyzed. / Este trabalho apresenta a avaliaÃÃo comparativa de trÃs inversores multinÃveis monofÃsicos com grampeamento do ponto central, baseados em cÃlulas de comutaÃÃo, que apresentam como caracterÃstica comum a elevaÃÃo da capacidade da corrente total de saÃda dos conversores sem aumentar os esforÃos de corrente nos semicondutores. A tÃcnica utilizada para realizar esta avaliaÃÃo consiste, primeiramente, na anÃlise individual da topologia clÃssica de trÃs nÃveis, aplicando apenas o paralelismo de cÃlulas de comutaÃÃo. Em seguida à realizada a anÃlise detalhada da principal topologia avaliada neste trabalho. Trata-se do inversor de cinco nÃveis com grampeamento do ponto central, baseado na cÃlula de comutaÃÃo de mÃltiplos estados, que utiliza conversores multinÃveis intercalados, acoplados magneticamente atravÃs de um autotransformador que, por sua vez, tem como finalidade distribuir uniformemente a corrente total de saÃda entre os enrolamentos e, consequentemente, entre os semicondutores do conversor. AlÃm de apresentar perdas de conduÃÃo reduzidas nos semicondutores, este conversor tambÃm apresenta uma reduÃÃo no volume e peso dos componentes magnÃticos, devido à frequÃncia de operaÃÃo dos elementos passivos possuir um valor mÃltiplo da frequÃncia de comutaÃÃo dos interruptores. Como consequÃncia, os conversores resultantes apresentam alto rendimento, alta densidade de potÃncia e uma baixa distorÃÃo harmÃnica total para a tensÃo e corrente de saÃda. A anÃlise teÃrica do inversor de cinco nÃveis com grampeamento do ponto central, baseado na cÃlula de comutaÃÃo de mÃltiplos estados, à verificada atravÃs de simulaÃÃo computacional e da experimentaÃÃo obtida a partir de protÃtipos desenvolvidos para uma potÃncia de 5 kW. SÃo tambÃm apresentados resultados de simulaÃÃo e experimentais para a terceira topologia analisada, o inversor de cinco nÃveis com grampeamento do ponto central, baseado em cÃlulas de comutaÃÃo intercaladas. Finalmente, à realizada uma avaliaÃÃo comparativa entre os trÃs inversores analisados.

Traction inverter, as a critical component in electrified transportation, has been the subject of many research studies in terms of topologies, modulation, and control schemes. Recently, some of the well-known electric vehicle manufacturers have utilized higher-voltage batteries to benefit from lower current, higher power density, and faster charging times. With the ongoing trend toward higher voltage DC-link in electric vehicles, some multilevel structures have been investigated as a feasible and efficient option for replacing the two-level inverters. Higher efficiency, higher power density, better waveform quality, and inherent fault-tolerance are the foremost advantages of multilevel inverters which make them an attractive solution for this application. The first contribution of this thesis is to investigate and present a comprehensive review of the multilevel structures in traction applications. Secondly, this thesis proposes an electro-thermal model based on foster equivalent thermal networks for a designed three-level active neutral point clamped (ANPC) inverter, as well as a modified sinusoidal pulse-width modulation (SPWM) -based technique. This electro-thermal model and the modulation technique enable temperature estimation in the inverter and minimization of the hotspot temperature and hence, increase the power density. Based on the experimental results derived from the implemented setup, a 12% increase in power density is achieved with the proposed technique. The other contribution is a reduced-complexity model-predictive controller (MPC) for the three-level ANPC inverter without weighting factors in which the number of calculations has dropped from 27 to 12 in each sampling period. The improvements to the structure and control system of the inverter are supported by theoretical analysis, simulation results, and experimental tests. A three-level inverter is implemented for 800 V, 70 kW operation and tested. 750 V Silicon Carbide (SiC) switches are utilized in the inverter structure. Finally, future trends and suggestions for the following studies are stated in this thesis. / Thesis / Doctor of Philosophy (PhD)

In high-power electric drives, multilevel inverters are generally deployed to address issues such as electromagnetic interference, switch voltage stress and harmonic distortion. The switching frequency of the inverter is always kept low, of the order of 1KHz or even less to reduce switching losses and synchronous pulse width modulation (PWM) is used to avoid the problem of sub-harmonics and beat frequencies. This is particularly important if the switching frequency is very low. The synchronous PWM is getting popularity as its realization is very easy with digital controllers compared to analog controllers. Neutral-point-clamped (NPC) inverters, cascaded H-bridge, and flying-capacitor multilevel inverters are some of the popular schemes used for high-power applications. Hybrids of these multilevel inverters have also been proposed recently to take advantage of the basic configurations. Multilevel inverters can also be realized by feeding the induction motor from both ends (open-end winding) using conventional inverter structures. For controlling the output voltage of these inverters, various PWM techniques are used. Chapter-1 of this thesis provides an over view of the various multilevel inverter schemes preceded by a discussion on basic two-level VSI topology. The inverters used in motor drive applications have to be operated in over-modulation range in order to extract the maximum fundamental output voltage that is possible from the dc-link. Operation in this high modulation range is required to meet temporary overloads or to have maximum power operation in the high speed range (flux weakened region). This, however, introduces a substantial amount of low order harmonics in the Motor phase voltages. Due to these low-order harmonic frequencies, the dynamic performance of the drive is lost and the current control schemes are severely affected especially due to 5th and 7th harmonic components. Further, due to these low-order harmonics and non-linear PWM operation in over-modulation region, frequent over-current fault conditions occur and reliability of the drive is jeopardized. The twelve sided-polygonal space vector diagram (dodecagonal space vectors) can be used to overcome the problem of low order 5th and 7th harmonics and to give more range for linear modulation while keeping the switching frequency at a minimum compared to conventional hexagonal space vector based inverters. Thus, the dodecagonal space-vector switching can be viewed as an engineering compromise between low switching frequency and quality load current waveform. Most of the previous works of dodecagonal space-vector generation schemes are based on NPC inverters. However, sophisticated charge control schemes are required in NPC inverters to deal with the neutral-point voltage fluctuation and the neutral-point voltage shifting issues. The losses in the clamping diodes are another major concern. In the second chapter, a multilevel dodecagonal space-vector generation scheme based on flying capacitor topology, utilizing an open end winding induction motor is presented. The neutral point charge-balancing problem reported in the previous works is not present in this scheme, the clamping diodes are eliminated and the number of power supplies required has been reduced. The capacitors have inherent charge balancing capability, and the charge control is done once in every switching cycle, which gives tight voltage control for the capacitors. For the speed control of induction motors, the space-vector PWM scheme is more advantageous than the sine-triangle PWM as it gives a more linear range of operation and improved harmonic performance. One major disadvantage with the conventional space-vector PWM is that the trigonometric operations demand formidable computational efforts and look-up tables. Carrier based, common-mode injected PWM schemes have been proposed to simplify the PWM process. However, the freedom of selecting the PWM switching sequences is limited here. Another way of obtaining SVPWM is using the reference voltage samples and the nearest vector information to switch appropriate devices for proper time intervals, realizing the reference vector in an average sense. In-formation regarding the sector and nearest vectors can be easily obtained by comparing the instantaneous amplitudes of the reference voltages. This PWM approach is pro-posed for the speed control of the motor in this thesis. The trigonometric operations and the requirement of large look-up tables in the conventional SVPWM are avoided in this method. It has the additional advantage that the switching sequences can be decided at will, which is helpful in reducing further, the harmonic distortion in certain frequency ranges. In this way, this method tries to combine the advantages of vector based methods (conventional SVPWM) and scalar methods (carrier-based methods). The open-end winding schemes allowed the required phase voltage levels to be generated quite easily by feeding from both ends of the windings. Thus, most of the multilevel inverters based on dodecagonal space-vector structures relied on induction motors with open-end windings. The main disadvantage of open-end winding induction motor is that six wires are to be run from the inverter to the motor, which may be unacceptable in certain applications. Apart from the inconvenience of laying six wires, the voltage reflections in the wires can lead to over voltages at the motor terminals, causing insulation failures. Where as the topology presented in chapter-2 of this thesis uses open-end winding motor with flying-capacitor inverters for the generation of dodecagonal space-vectors, the topology presented in chapter-3 utilizes a cascade connection of flying-capacitors and floating H-bridge cells to generate the same set of voltage space-vectors, thus allowing any standard induction motor as the load. Of the methods used for the speed control of induction motors, namely sine-triangle PWM and space vector PWM, the latter that provides extra modulation range is naturally preferred. It is a well-understood fact that the way in which the PWM switching sequences are applied has a significant influence on the harmonic performance of the drive. However, this topic has not been addressed properly for dodecagonal voltage space-vector based multilevel inverter drives. In chapter-4 of the thesis, this aspect is taken into ac-count and the notion of “harmonic flux trajectories” and “stator flux ripple” are used to analyze the harmonic performance of the various PWM switching schemes. Although the PWM method used in this study is similar to that in chapter-2, the modification in the PWM switching sequence in the PWM algorithm yields significant improvements in harmonic performance. The proposed topologies and PWM schemes are extensively simulated and experimentally verified. The control scheme was implemented using a DSP processor running at a clock frequency 150MHz and a four-pole, 3.7kW, 50Hz, 415V three-phase induction motor was used as the load. Since the PWM ports are limited in a DSP, a field-programmable gate array (FPGA) was used to decode the PWM signals from the DSP to generate timing information required for PWM sequencing for all the power devices. The same FPGA was used to generate the dead-time signals for the power devices also.

Submitted by Emanuel Varela Cardoso (emanuel.varela@ufcg.edu.br) on 2018-08-28T20:15:07Z No. of bitstreams: 1 DIEGO ALBERTO ACEVEDO BUENO – DISSERTAÇÃO (PPGEEI) 2015.pdf: 8647076 bytes, checksum: c16b323a227c1c3224d8f023324db513 (MD5) / Made available in DSpace on 2018-08-28T20:15:07Z (GMT). No. of bitstreams: 1 DIEGO ALBERTO ACEVEDO BUENO – DISSERTAÇÃO (PPGEEI) 2015.pdf: 8647076 bytes, checksum: c16b323a227c1c3224d8f023324db513 (MD5) Previous issue date: 2015-08 / CNPq / Esta dissertação examina seis topologias hibridas assimétricas com acoplamento magnético. O termo topologia hibrida assimétrica se refere a qualquer topologia que combine os princípios das topologias clássicas com duas fontes de tensão isoladas ou mais com tensões diferentes. Das topologias propostas, quatro possuem saída única conectada ao ponto intermediário do barramento e as restantes dispõem de saída diferencial usando outro braço de dois níveis. Para simplificar o estudo destas topologias, desenvolveu-se um modelo elétrico e magnético detalhado dos indutores acoplados usando componentes de modo comum e diferencial. Posteriormente, esse modelo foi inserido no modelo do conversor para o desenvolvimento de uma estratégia de controle da corrente de saída e da corrente de modo diferencial garantindo a operação em modo de condução continua com número reduzido de componentes. Os modos de operação e as respectivas estratégias de modulação são apresentados. Além disso, o efeito da diferença das tensões de polo máximas sobre o desempenho dos conversores e na escolha do indutor acoplado foi analisado. Para avaliar o desempenho destas topologias, foram realizadas simulações com os modelos completos das chaves e dos diodos usando o software PSIM fixando a potência de saída para todas as topologias em 1 kVA. Também, alguns resultados experimentais em malha aberta são apresentados para validar os modelos desenvolvidos / This paper examines six asymmetric hybrid topologies with magnetic coupling. The term “asymmetric hybrid topology” refers to any topology that combines the principles of classical topologies with two isolated voltage sources or more with different voltages. From these topologies, four have single-ended output connected to the midpoint of dc-link and the remaining has differential output employing another two-level arm. To simplify the analysis, a detailed electric and magnetic model of the coupled inductors was developed appealing to common- and differential-mode components. Subsequently, this model was inserted into the model of the converter for developing a control strategy for the output and the differential mode currents, ensuring the operation in continuous conduction mode with a reduced number of components. The modes of operation and the modulation strategies are presented. In addition, the difference of the maximum pole voltages was analyzed for determining its effect on the converter performance and the coupled inductor selection. To evaluate the performance of these topologies, simulations were performed with the complete models of switches and diodes using the PSIM software by setting the output power at 1 kVA for all topologies. Also, experimental open loop results are presented to validate the developed models.

Submitted by Emanuel Varela Cardoso (emanuel.varela@ufcg.edu.br) on 2018-09-21T17:18:48Z No. of bitstreams: 1 JOÃO HELDER GONZAGA MUNIZ DA SILVA - DISSERTAÇÃO (PPGEEI) 2016.pdf: 5964138 bytes, checksum: e0f1b793c6851d1c5ab1ec454862dfae (MD5) / Made available in DSpace on 2018-09-21T17:18:48Z (GMT). No. of bitstreams: 1 JOÃO HELDER GONZAGA MUNIZ DA SILVA - DISSERTAÇÃO (PPGEEI) 2016.pdf: 5964138 bytes, checksum: e0f1b793c6851d1c5ab1ec454862dfae (MD5) Previous issue date: 2016-11-14 / Os inversores multiníveis foram introduzidos como uma alternativa para o aumento da qualidade e da eficiência dos sistemas alimentados por inversores. Dependendo do nível de tensão c.c. do barramento aplicado ao inversor, pode ser inevitável a utilização de topologias multi-níveis. Estas topologias possibilitam a redução da tensão sobre cada um destes dispositivos. Contudo, uma quantidade maior de interruptores não só aumenta o custo final do inversor, como também requer o uso de estratégias mais complexas de modulação e controle. Ainda, alguns pontos inerentes aos inversores multiníveis como: redução da tensão de modo-comum, tolerância à faltas e desbalanceamento das tensões dos capacitores, entre outros, precisam ser investigados. Neste cenário, são de muito interesse os estudos de novas topologias multiníveis, além de novas técnicas de modulação simplificadas. Neste trabalho serão estudados inversores multiníveis com diferentes princípios de operação, abordando topologias híbridas formadas pelo empilhamento de células dois níveis. A primeira delas, consiste de um inversor monofásico de quatro níveis em ponte. Este inversor é composto de um braço de dois níveis e um braço de três níveis apresentando mesma tensão de bloqueio para todas as haves. Na segunda topologia, os pontos centrais de cada um dos braços são conectados ao mesmo ponto, com o braço externo envolvendo o interno, representando uma estrutura pouco investigada. Esta topologia necessita de chaves bidirecionais para tornar possível seu correto funcionamento. É feito ainda um estudo de um inversor de 2/3 níveis, onde é proposto um algoritmo de modulação simplificado, onde consegue-se uma significativa redução no número de operações realizados. Por fim, é estudado um inversor multinível simétrico híbrido baseado nas topologias meia-ponte e ANPC, onde são propostas duas alterações na topologia que juntamente com a modificação do padrão de chaveamento, fornece um melhor controle no balanceamento das tensões dos capacitores, além de reduzir a quantidade de fontes c.c. utilizadas pelo mesmo. / Multilevel inverters are an alternative for both quality and efficiency increase of inverter fed systems. Depending on the voltage level c.c. of the bus applied to the inverter, the usage of multilevel topologies is inevitable. Those topologies reduce the voltage over each of those devices. However, a higher quantity of switches increases the inverters final cost, and requires more complex approaches for control and modulation. Also, few inherent aspects of the multilevel inverters including: reduction of the common-mode voltage, fault tolerance and unbalance capacitors voltages, among other, need to be investigated. In this scenario, new multilevel topologies have great interest, also with new and simplified modulation techniques. In this work we study multilevel inverter with different operational principles, formed by formed by stacking two levels cells. The first one, consist of a single-phase inverter with a four level bridge. This inverter is composed of a two level leg and a three level leg, presenting the same blocking voltage for all the switches. In the second topology, every central point of each of the leg is connected into a common single point, with the extern leg over the intern one, a structure poorly studied. This topology needs bidirectional switches for a correct well function. A study of the 2/3 level inverter is done, in which a signicant redution of the operation numbers is a chieved. Finally, a hybrid symmetricmultilevel inverter is studied based on both half-bridge and ANPC topologies, in which two changes in the topology are proposed alongside with some changes in the switching standard. This provides a better control in the capacitors voltage balance, and reduces the amount of sources c.c. used by them.

Thesis submitted in fulfilment of the requirements for the degree Doctor of Technology: Electrical Engineering in the Faculty of Engineering at the Cape Peninsula University of Technology / This research focuses on the predictive current control of multilevel converters with the aim of providing an optimized system for three-phase, multilevel inverters (MLIs) so that the load current and the voltage of the capacitors can be controlled. A model predictive current control algorithm is proposed, specifically directed at the utilisation of power obtained from renewable energy systems (RESs). The model was developed for three-phase, multilevel voltage source inverters (MLVSIs), three-phase, three-level diode-clamped converters (DCCs) and flying capacitor converters (FCCs). In this study the renewable energy systems model is used to investigate system performance when power is supplied to a resistiveinductive load (RL-load). The proposed control method was split into two different control algorithms. Firstly, a finite set-model predictive current control (FS-MPCC) method was developed to control the output current of three-phase, MLIs. This control method was selected to reduce the calculation effort for model predictive control (MPC) and to increase the possible prediction horizon. Secondly, to solve the flying capacitor voltage balance problem in an FCC, as well as to solve the DC-link capacitor voltage balance problem in a DCC, a hysteresis-voltage alancing algorithm based on predictive control, was designed—this algorithm was used to keep the flying capacitor voltages and DC-link capacitor voltages within their hysteresis bands. Finally, for some classes of power converters, a performance evaluation of the FS-MPCC method for three-phase, three-level MLIs was investigated in terms of power quality and dynamic response. The improvement was assessed in terms of total harmonic distortion (THD) of the output voltage for the RL-load. The modelling and co-simulation were carried out using MATLAB/Simulink with PSIM software. The co-simulation results indicated that the proposed control algorithms achieved both high performance and a high degree of robustness in RESs applications.

CoordenaÃÃo de AperfeiÃoamento de Pessoal de NÃvel Superior / Diante da necessidade em aperfeiÃoar as tecnologias existentes para a conversÃo de energia elÃtrica em sistemas de alta potÃncia, este trabalho tem por finalidade projetar, analisar e implementar experimentalmente uma tÃcnica de modulaÃÃo com o intuito de reduzir o conteÃdo harmÃnico da tensÃo de saÃda em um inversor multinÃvel com capacitor flutuante de trÃs nÃveis. Algumas das diversas tÃcnicas de modulaÃÃo (PSPWM, LSPWM, HE-PWM e CSV-PWM) foram analisadas e implementadas no controlador digital FPGA a fim de comparar suas caracterÃsticas de desempenho com a tÃcnica de modulaÃÃo proposta. AlÃm disso, foi realizado o estudo de perdas da topologia de inversor multinÃvel com capacitor flutuante de trÃs nÃveis e a anÃlise teÃrica da distorÃÃo harmÃnica total da modulaÃÃo proposta. Finalmente, o desenvolvimento digital das tÃcnicas mostrou resultados coerentes, com formas de onda obtidas experimentalmente com alta qualidade de resoluÃÃo. A comparaÃÃo entre as estratÃgias de modulaÃÃo em termos de DHT resultou positivamente à modulaÃÃo proposta, cujos resultados experimentais de DHT nas tensÃes de linha na saÃda apresentaram o melhor desempenho para toda a faixa de Ãndices de modulaÃÃo comparadas Ãs tÃcnicas PSPWM, LSPWM-POD e CSV-PWM e uma reduÃÃo de atà 4,5% em relaÃÃo à HE-PWM. Isto comprova o estudo teÃrico realizado e sua aplicaÃÃo no inversor multinÃvel com capacitor flutuante de trÃs nÃveis. / Given the need to improve the existing technologies for electrical energy conversion into high power systems, this works purpose to design, analyze and implement a modulation technique that aims to reduce the output voltage harmonic content on the three-level flying capacitor multilevel inverter. Some of the various conventional modulation techniques (PSPWM, LSPWM, HE-PWM e CSV-PWM) have been analyzed and implemented in FPGA controller in order to compare their performance features with the proposed modulation technique. Furthermore, the losses study of the three-level flying capacitor multilevel inverter topology and the total harmonic distortion theoretical analysis of the proposed modulation technique have been made. Finally, the digital implementation of the techniques showed consistent results with experimentally obtained waveforms with high quality resolution. The comparison between the modulation strategies in the THD rates resulted positively for the proposed modulation, which THD experimental results in the line output voltage showed the best performance for all range of modulation indexes compared to techniques PSPWM, LSPWM-POD and CSV-PWM and the reduction of up to 4.5% better than HE-PWM. This proved the theoretical study done and its application in three-level flying capacitor multilevel inverter.

Use of multilevel inverters are inevitable in medium and high voltage drives. This is due to the fact that the multilevel inverters can produce voltages in smaller steps which will reduce the harmonic content and result in more sinusoidal voltages and currents as compared to voltages and currents from two-level inverters. Due to the device limitations, use of two-level inverters is not possible in medium and high voltage drive applications. Though multiple devices can be connected both in series and parallel to achieve two-level operation, the output voltages still suffer from high harmonic content. Multilevel inverters have multiple DC voltage levels with switches that enable one of the voltage steps to be applied to the load. Due to decrease in step size during each switching instant, output voltages and currents of the multilevel inverters have considerably less harmonic content. As the number of levels increase, the switching step reduces thereby the harmonic content also reduces drastically. Due to their advantages, multilevel inverters have gained lot of acceptance in the industry even at lower voltages. The three main configurations that have gained popularity are the neutral point clamped converter, the flying capacitor converter and the cascaded H-bridge converter. Each converter has its own set of advantages and disadvantages. Based on the requirements of various applications, it is possible to fabricate hybrid multilevel topologies that are combinations of the three basic topologies. Researchers around the world have proposed several such converters for diverse applications so as to suit particular requirements like modularity, ease of control, improved reliability, fault tolerant capability etc. The present thesis explores multilevel converters with single DC link to be used for motor drive and grid connected applications. A novel five-level inverter topology formed by cascading a floating capacitor H-bridge module to a regular three-level flying capacitor inverter has been explored in chapter 2. The three-level flying capacitor inverter can generate pole voltages of 0, VDC /2 and VDC . By cascading it with another floating capacitor H-bridge of voltage magnitude VDC /4, pole voltages of 0, VDC /4, VDC/2, 3VDC /4 and VDC . Each of these pole voltage levels can have one or more switching combinations. However each switching combination has a unique effect on the state of the two capacitor voltages. By switching through redundant switching combinations for the same pole voltage, the two capacitors present in each phase can be balanced. The proposed topology also has an advantage that if one of the devices in the H-bridge fails, the topology can still be operated as a regular three-level flying capacitor inverter that can supply full load at rated power by bypassing the faulty H-bridge. This fault tolerant operation of the converter will enable it to be used in applications like traction and marine drives where high reliability is needed. The proposed converter needs a single DC link. All the required voltage levels can be generated from the single DC link. This enables back to back grid connected operation possible where multiple converters can interact with a single DC link. Various pole voltage switching combination and its effect on individual capacitor has been studied. A control algorithm to balance the capacitor voltages by switching through multiple redundancies for the same pole voltage has been developed. The proposed configuration has been implemented in hardware using IGBT H-bridge modules and the control circuitry is realized using DSP and FPGA. The performance of the drive is verified for various frequencies and modulation indices during steady state by running a three phase induction motor at no load. The stability of the drive during transients has been studied by accelerating the machine suddenly at no load and analyzing the performance of the drive. The capacitor voltages are made to deviate from their intended values and the capacitor balancing algorithm has been verified for its ability to bring the capacitor voltages back to their intended values. The experimental results have been presented and discussed in detail in the chapter 2. In the third chapter a common-mode voltage eliminated three-level inverter using a single DC link has been proposed. The power schematic is similar to the one presented in chapter 2. In this chapter the space vector polygon formed by the three phases of the proposed topology has been presented. The common-mode voltage generated by different pole voltage combinations for same space vector location and the redundant switching state combinations has been studied. The pole voltage combinations with zero common mode voltage have been studied. The switching state redundancies for the the pole voltage have been studied. The space vector polygon formed with the pole voltage combinations has been analyzed. A drive is made with the proposed common-mode voltage eliminated inverter. The performance of the drive is tested for various modulation indices and frequencies by running a three phase squirrel cage induction motor at no load. The transient performance is verified by accelerating the motor suddenly and checking the common-mode voltage along with the capacitor voltages. The results have been presented and discussed in detail in chapter 3. This converter has advantages like use of single DC supply, ability to operate as a regular three level converter in case of failure of one of the H-bridges. The work presented in fourth chapter proposes a novel three phase 17-level inverter configuration which utilizes a single DC supply. The rest of voltages are generated using three floating capacitor H-bridges. The redundant switching combinations for generating various pole voltages and their effect on the capacitors have been studied and suitable capacitor balancing algorithm has been developed. The proposed topology has been realized in hardware and the performance of the drive during steady state has been studied by running an induction motor at various modulation indices and frequencies. The transient response of the drive has been observed by accelerating the motor suddenly under no load. The results have been presented in detail in chapter four. This configuration also needs a single DC link. The advantages of this configuration is in case of failure of any devices in the H-bridge, the drive can be operated at reduced number of levels while supplying full load current. This feature helps the drive to be used in fault tolerant applications like marine and traction drives where reliability of the drive is of prime importance. All the topologies that have been presented in the previous chapters have mentioned about the usage of the proposed genre of topologies use single DC link and hence will enable back to back grid tied inverter connection. In the fifth chapter this has has been verified experimentally. The three phase squirrel cage induction motor is driven by using the seventeen-level inverter drive proposed in chapter four. A five-level active front-end is realized by the converter topology proposed in chapter two. The converter is run and the performance of the drive is studied at various modulation indices and speeds of the motor. Various aspects like re-generation operation, acceleration and other aspects of the drive have been studied experimentally and the results are presented in detail. For experimental setup, Semikron SKM75GB12T4 IGBT modules have been used to realize the power topology. These IGBTs are driven by M56972L drivers. The control circuit is realized using TMS320F2812 DSP along with Xilinx Spartan 3 FPGA (XC3S200) has been used. The voltages and currents are sensed using LEM LV-20P and LA 55-P hall effect based sensors.

Coordenação de Aperfeiçoamento de Pessoal de Nível Superior / This Ph.D. Thesis proposes a comparison of modulation techniques, semiconductors devices technologies and topologies for multilevel inverters, in order to point out the multilevel drive system that presents the best performance for a given application. Initially, a comparison methodology is proposed which is based on selecting the switching frequency where all systems present 99% efficiency. The performance indeces included in this analysis are: semiconductor devices power losses, heat-sink volume, THD, DF1, DF2, common mode voltage and harmonic spectrum. For each topology of multilevel inverter it is made a comparison among the modulation techniques and semiconductor devices to obtain the set (modulation + semiconductor) that presents better overall performance. After, the comparisons for each topology, a comparison among the sets that present better results is made, leading to the choice of the best system for a given specific application. The modulation techniques that present the best performance for each multilevel inverter are implemented on an FPGA. Experimental results, such as inverters efficiency and output voltage waveform, are presented for a reduced scale prototype, with the intention of validating the models employed in this Phd Thesis. / Esta Tese de Doutorado propõe a comparação de técnicas de modulação, tecnologias de dispositivos semicondutores e topologias de inversores multiníveis, para realizar o apontamento do sistema de acionamento de média tensão que apresenta melhor desempenho para uma dada aplicação. Inicialmente é proposta uma metodologia de comparação, que tem como objetivo encontrar a frequência de comutação na qual cada sistema apresenta 99% de rendimento. Os índices de desempenho propostos para análise são: perdas nos dispositivos semicondutores, volume do dissipador, THD, DF1, DF2, tensão de modo comum e espectro harmônico. Para cada topologia de inversor multinível é efetuada uma comparação entre as técnicas de modulação e os dispositivos semicondutores selecionados, para determinar o conjunto (modulação + semicondutor) que apresentam os melhores resultados nos índices de desemplenho supracitados. Após as comparações para cada topologia, é realizada uma comparação entre os conjuntos que apresentaram melhor resultado, levando ao apontamento do sistema mais adequado para uma dada aplicação. As técnicas de modulação que apresentaram melhor desempenho para cada inversor multinível são implementadas em FPGA. Os resultados experimentais como rendimento dos inversores e formas de onda das tensões de saída são apresentados para protótipos de escala reduzida, objetivando validar alguns dos modelos empregados na Tese.

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