Cascaded H-bridge (CHB) multilevel inverters have significant popularity with motor drives applications due to their modularity, scalability, and reliability. Typical CHB inverters employ diode rectifiers that allow unidirectional power flow from the grid to the load. To capture and utilize the regenerated energy in regenerative applications, regenerative CHB drives were introduced with two-level voltage source converters in the front end to allow bidirectional energy flow. This solution is accompanied by challenges of high number of switches and control circuits, high switching power losses, and massive dimensions. Recently, developing more economic versions of regenerative cascaded H-bridge drives has become one of the hottest topics in power electronics research. In this thesis work, two solutions are proposed for more energy efficient and economic regenerative CHB drives. The first solution is a proposed power cell configuration that reduces the number of switches per cell by two. Additionally, phase alternation connection method and carrier phase-shifting techniques are introduced to address the challenges of the presented configuration. The switch-count reduction reduces the system’s complexity, switches’ cost, and footprint. The second proposed solution is a new controller to operate the front-end converters as fundamental frequency ends (FFEs). The proposed controller is employed in both the conventional regenerative cascaded H-bridge and the proposed reduced switch-count configuration. This solution minimizes the switching power losses, and results in more compact and economic design, with higher DC-link utilization. Theoretical analysis and simulation studies of both proposed solutions show promising performance and capability to be applied as energy-efficient and cost effective regenerative CHB motor drives. Experimental validation of the proposed reduced switch-count configuration is presented for STATCOM operation of a scaled-down 7-Level regenerative CHB drive system. The future work of this thesis includes experimental validation of the proposed FFE controller, and operation of the system with regenerative motor load. / Thesis / Master of Applied Science (MASc)

High power converters are widely used in many industries. At power levels in the range of Mega Watt (MW), power conversion at medium voltage (MV) is preferred due to better efficiency and lower cost. For medium voltages applications, multilevel converters are widely adopted due to the features they offer with respect to two-level converters. Cascaded H-bridge topology is a widely adopted multilevel topology because of its modularity, scalability, and reliability. The conventional cascaded H-bridge topology allows two-quadrant operation. In order to allow fourquadrant operation, an active front end version of the cascaded H-bridge topology has been proposed in literature and recently commercialized. In the field, power converters operates under harsh loading and environmental conditions. The resulting stresses imposed on converter components cause their gradual degradation. In cascaded H-bridge converters, typically power cell components such as power modules, DC-bus capacitors, and control PCBs are v highly stressed. Under these stresses power cell components degrade and require replacement in the field, otherwise unexpected failures may occur. The thesis aim is to address power cell components reliability through proposing novel regenerative cascaded H-bridge converter control schemes to reduce components stresses and failure probability without increasing size, cost, or complexity. First, a novel PWM active front end control scheme has been proposed to reduce the inherent ripple current stresses on the DC-bus capacitors. Second, the thesis proposes a novel grid or near grid switching frequency front end control scheme to reduce stresses on power modules and the power cell cooling requirements. Third, novel cascaded H-bridge front end control schemes are proposed to reduce the sensor count, thereby decreasing failure rate and cutting down cost. The proposed work has been thoroughly validated through detailed 9- cell regenerative cascaded H-bridge system simulation and experimentation. / Thesis / Doctor of Philosophy (PhD)

MU LT I L E V E L inverters are becoming the preferred choice for medium voltage high power applications. Multilevel inverters have a number of inherent advantages over conventional two level inverters. The output voltage has multiple steps or levels, resulting in reduced dV/dt, which leads to lower electromagnetic interference, making it easier to meet electromagnetic compatibility (EMC) regulations. Multilevel inverters have a much lower effective switching frequency, which leads to a reduction in switching losses. The output voltage of multilevel inverters has a much lower harmonic content. In applications such as power conversion or grid-connection, filters need to be much smaller, or can be eliminated. In motor drive applications, the low harmonic content results in smoother, ripple-free shaft torque. The neutral-point clamped (NPC), cascaded H-bridge (CHB) and flying capacitor (FC) topologies were among the earliest multilevel topologies. NPC topologies require additional clamping diodes to clamp the output to the DC bus midpoint. CHB topologies use a number of isolated DC suplies to generate multilevel output. FC topologies work with a single DC link but use additional floating capacitors. Since then, a number derivatives and improvements to these topologies have been proposed. Topologies with low switch counts are desirable because of the corresponding reduction in system size and cost. A low total component count is also desirable since it results in better reliability. Induction motors in high power applications are often operated in the open-end configuration. Here, the start terminals of the motor phase windings are connected to one three phase inverter, while the end terminals are connected to a second three-phase inverter. The two inverters are typically powered by isolated supplies to prevent the flow of common mode currents through the motor. The open end configuration has a number of advantages It can be used with nearly all high power motors with no need for electrical or mechanical modification, since all six winding terminal are available externally. The two inverters driving the open-end motor are effectively cascaded. As a result, two inverters of lower voltage and power rating can replace a single inverter with higher voltage and power rating. In addition, if one of the inverter fails, it can be bypassed and the system can be operated at reduced power. In many applications such as heating, ventilation and air conditioning (HVAC), the load power is proportional to the cube of the shaft speed, so a 50% reduction in power translates to only 20% reduction in speed, thereby improving overall system reliability. The cascading of inverters also enables multilevel operation, which is exploited for the topologies proposed in this thesis. In the open-end configuration it is important to ensure that both the DC supplies deliver power to the load. Otherwise, power can circulate through the motor windings. In addition, if the two inverters are powered by rectifier supplies, the DC bus of one inverter can charge uncontrollably, resulting in distortion of phase voltages and currents. If DC bus overcharging continues unchecked the DC bus voltage can even exceed the system rating, resulting in permanent damage. This thesis proposes two novel topologies for open-end induction motor drives with low switch counts. Both topologies are powered by two unequal, isolated DC sources having DC voltages in a 3:1 ratio. Multiple levels in the output voltage are obtained using a number of floating capacitors in each phase. Modulation and control schemes are also proposed for both topologies to ensure that DC bus overcharging never occurs, while all the capacitor voltages are kept balanced at their nominal values. The first of these two topologies is a nine level inverter for open end induction motor drives. It consists of two three-level flying capacitor inverters connected to the induction motor in the open end configuration. The two inverters are powered by DC sources of voltage 6VDC/8 and 2VDC/8, which generates an effective phase voltage having nine levels in steps of VDC/8. This topology has only eight switches and two floating capacitors per phase. The space vector structure for this topology is hexagonal, and has 217 space vector locations. A space-vector based formulation is used to determine the pole voltage of the inverter such that DC bus over charging is prevented. In addition, selection of switching states is used to balance the voltages of all floating capacitors. This scheme allows the floating capacitors to be charged up during system startup, thereby eliminating the need for separate pre-charging circuitry. A level-shifted carrier PWM based modulation scheme has been developed, which can be used with both scalar and vector control schemes. The gating signal for switches turning on must be delayed by a small amount (to allow the complementary switch to turn of), failing which current shoot through can occur. This delay is called dead time, during which gate signals to both complementary devices are turned of. Under certain conditions in the flying capacitor topology, the pole voltage can contain large undesirable transients during the dead time which result in phase current distortion, and electromagnetic noise. A novel scheme to eliminate this problem is proposed using a digital state machine approach. The switching state for each subsequent switching interval is determined based on the present switching state such that the pole voltage does not contain a transient, without affecting the phase voltage of the inverter, and irrespective of the current magnitude or direction. The state machine was implemented using an FPGA, and required an additional computation time of just 20ns, which is much smaller than the inverter dead time duration of typically 2.5µs. The second novel topology proposed in this thesis is a seventeen level inverter for an open end induction motor drive. Here, one three-level inverter and one seven-level inverter are connected to the two ends of the induction machine. The three-level inverter is a flying capacitor inverter. The seven-level inverter is a hybrid topology – it consists of an H-bridge cascaded to each phase of a three level flying capacitor inverter. This scheme is also powered by two isolated DC sources in 3:1 ratio with magnitudes 12VDC/16 and 4VDC/16. The effective phase voltage has seventeen levels in steps of VDC/16. This topology has a total of twelve switches and three floating capacitors per phase. The space vector structure for this topology is hexagonal, and has 817 space-vector locations. Space vector analysis was used to determine the pole voltages, and the switching states such that DC bus overcharging is prevented while also balancing the voltages of the floating capacitors. A non-iterative algorithm was developed for determining the switching states, suitable for implementation in digital logic using an FPGA. The scheme is able to charge the all capacitors at startup as well, eliminating the need for separate pre-charging circuits. Hardware prototypes were built for both the topologies described above for experimental verification, and used to drive a three phase 50Hz, 1.5kW, four pole induction motor in V/f control mode. The inverters topologies were built using 1200V, 75A IGBT half-bridge modules (Semikron SKM75GB12T4) with hybrid opto-isolated gate drivers (Mitsubishi M57962). Three phase rectifiers were used to create the asymmetric DC supplies Hall effect sensors were used to sense the DC link and floating capacitor voltages and phase currents (LEM LV20P voltage sensors and LA55 current sensors). Signal conditioning circuitry was built using discrete components. The PWM signals and V/f controller were implemented using a digital signal processor (Texas Instruments TMS320F28335). Synchronous PWM with was used to eliminate sub-harmonics from the phase voltage, and to ensure three-phase and half-wave symmetry. The internal ADC of the DSP was used for sampling all voltages and currents. The remaining digital logic for switch state selection was implemented on a FPGA (Xilinx Spartan3 XC3S200). Dead time functionality was also implemented within the FPGA, eliminating the need for separate dead time hardware. Both topologies were first tested for steady state operation over the full modulation range, and the pole voltages, phase voltages and phase currents were recorded. System startup, and the ability of the controllers to balance all the capacitors at startup was tested next. The capacitor voltages were also observed during sudden loading, by quickly accelerating the motor. Finally, the phenomenon of DC bus overcharging was also demonstrated. These results demonstrate the suitability of the proposed topology for a number of applications, including industrial drives, alternate energy systems, power conversion and electric traction.

CoordenaÃÃo de AperfeiÃoamento de Pessoal de NÃvel Superior / Visando superar os desafios inerentes à conversÃo de energia elÃtrica em sistemas de alta potÃncia, minimizando as perdas e melhorando a qualidade da energia processada, este tra-balho tem por objetivo analisar e implementar uma tÃcnica de modulaÃÃo para ser aplicada nas duas topologias de inversores multinÃveis mais disseminadas - com neutro grampeado (NPC), e com capacitor flutuante (FC) - a fim de reduzir os esforÃos nos semicondutores, bem como melhorar o Ãndice de distorÃÃo harmÃnica da tensÃo de saÃda. Ao longo do trabalho foi evidenciada a necessidade da digitalizaÃÃo da tÃcnica proposta, visto que o desenvolvimento analÃgico da mesma acarretaria em um circuito complexo e de baixa confiabilidade. Dessa forma, escolheu-se como plataforma digital um FPGA, devido à sua facilidade de programa-ÃÃo e reconfiguraÃÃo, alÃm da alta velocidade e quantidade de pinos de entrada e saÃda. AlÃm da tÃcnica proposta, foram tambÃm desenvolvidas outras modulaÃÃes para fins de compara-ÃÃo, apresentando os padrÃes de chaveamento para cada uma delas, bem como o comporta-mento da corrente atravÃs dos semicondutores em cada perÃodo de chaveamento. Foi tambÃm realizada a anÃlise teÃrica das topologias e suas respectivas etapas de operaÃÃo, caracterÃsticas e levantamento das equaÃÃes que ditam a anÃlise das perdas para as diferentes situaÃÃes de tÃcnicas aplicadas a cada uma das estruturas. O desenvolvimento digital das tÃcnicas mostrou-se correta atravÃs da anÃlise das formas-de-onda colhidas por meio de um circuito digital-analÃgico. AlÃm disso, a comparaÃÃo da aplicaÃÃo dessas modulaÃÃes em inversores a trÃs nÃveis NPC e FC de 6 kW mostrou-se favorÃvel à tÃcnica proposta em termos de eficiÃncia e reduÃÃo da distorÃÃo harmÃnica em ambas as topologias, comprovando sua utilidade em con-versores multinÃveis de alta potÃncia. Por fim, foi apresentado o desenvolvimento da tÃcnica proposta em inversores com mais de trÃs nÃveis, onde se pode comprovar sua eficiente aplica-ÃÃo para tais fins, bem como sua expansibilidade para inversores de n nÃveis. / In order to overcome the challenge of processing electric energy in high power systems with minimal losses and high energy quality, this work presents the implementation and anal-ysis of a modulation technique applicable on both most well-known multilevel inverter struc-tures - neutral point-clamped (NPC), and flying capacitors (FC) - to reduce the stresses across the semiconductors devices, and to improve the total harmonic distortion of the output volt-age. Throughout the work, the necessity to digitalize the proposed technique has been evi-denced due to the high complexity and low reliability inherent to the analogical approach. Thus, the digital controller FPGA has been chosen, as it is easy to program and reconfigure, works at high speed, and has a lot of input and output pins. Additionally, other modulation techniques were also implemented to compare their performance with the proposed one, pre-senting the switching patterns and the behavior of the electrical currents through the semicon-ductors for each modulation. A theoretical analysis was also performed for both topologies and their respective operation principle, characteristics, and equations used on the losses anal-ysis for the different combinations of modulation applied to each structure. Finally, the digital development of the various techniques has proved to be correct by observing the waveforms obtained through the digital/analogical circuit. Besides, the comparison of the modulation techniques on 6 kW NPC and FC three-level prototype inverters proved to be favorable to the proposed technique in terms of efficiency and total harmonic distortion reduction on both topologies, confirming its usefulness on high power multilevel converters. At last, it was pre-sented the application of the proposed modulation technique to inverters with more than three levels, where it was observed its eligibility for n-levels topologies.

Made available in DSpace on 2015-03-03T15:07:32Z (GMT). No. of bitstreams: 1 LivianeCAM.pdf: 2271497 bytes, checksum: 4d8763a73b7fec60ad7f311e565d45b3 (MD5) Previous issue date: 2008-11-19 / Coordena??o de Aperfei?oamento de Pessoal de N?vel Superior / This work presents contributions in the detection and identication of faults in multilevel inverters through the study of the converters behavior under these operation conditions. Basically, the approached fault consists of an open-circuit in any switch of a three-level clamped diode inverter. The converter operation is characterized in the pre and post-fault states. A wave form behavior analysis of the pole voltage, phase current and dc-bus current is also done, which highlights characteristics that allow the detection of failure and, even, under favorable conditions, the identication of the faulty device. A compensation strategy of the approached fault (open-switch) is also investigated with the purpose of maintaining the driving system operational when a failure occurs. The proposed topology uses SCRs in parallel with the internal switches of the inverter, which allows, in some occasions, the full utilization of the dc-bus / Este trabalho apresenta contribui??es para a detec??o e identica??o de faltas em inversores multin?veis, baseado no estudo do comportamento desse conversor sob essas condi??es de opera??o. Basicamente, a falta abordada consiste na abertura n?o comandada de uma das chaves de um inversor de tens?o de tr?s n?veis com diodos de grampeamento. O funcionamento do conversor ? caracterizado nos estados de pr? e p?s-falta. ?, tamb?m, feita uma an?lise dos comportamentos das formas de onda das tens?es de p?lo, corrente de fase e correntes do barramento CC, as quais apontam caracter?sticas que possibilitam detectar falta e, ainda, em condi??es favor?veis, identificar o dispositivo que apresentou defeito. Uma estrat?gia de compensa??o da falta abordada (chave aberta) tamb?m ? investigada, com o prop?sito de manter a continuidade de funcionamento do sistema de acionamento, quando da ocorr?ncia de uma falha. A topologia proposta utiliza SCRs em paralelo com as chaves internas do inversor, a qual permite, em algumas ocasi?es, a total utiliza??o do barramento CC

FundaÃÃo Cearense de Apoio ao Desenvolvimento Cientifico e TecnolÃgico / This work deals with the theoretical analysis, design methodology and laboratory implementation of a 3kVA on-line mode Uninterruptible Power Supply (UPS) composed by a multilevel inverter based on a transformer with multiple secondaries and an active power factor correction input stage composed by a diode rectifier in series with a boost converter.The main motivation for this study is to assess the benefits of multilevel inverters in low power (<10kVA) applications. A 3kVA Uninterruptible Power Supply (UPS) with output and input voltage of 220V and 60Hz, has been implemented. Simulation and experimental results for a single phase prototype are conducted to validate the proposed idea. The utilization of low frequency operation inverters promotes low EMI, lower switches stresses, very low commutation losses and consequently higher efficiency. The multilevel converter here used isolates the load from the grid due to the multi-windings transformer intrinsic to the topology. The on-line mode of the UPS (no battery mode) has been implemented. Simulation and experimental results for a single-phase prototype are presented to validate the proposed converter. The UPS presented an efficiency of 90% / Este trabalho apresenta a anÃlise teÃrica, metodologia de projeto e implementaÃÃo do modo rede de um sistema ininterrupto de energia (UPS) na configuraÃÃo on-line, utilizando um inversor multinÃvel e um prÃ-regulador com correÃÃo de fator de potÃncia. O inversor baseia-se num transformador que opera em baixa freqÃÃncia com mÃltiplos secundÃrios isolados, em que a tensÃo multinÃvel na saÃda à formada atravÃs da combinaÃÃo dos enrolamentos secundÃrios do transformador por chaves de potÃncia estÃticas operando em baixa freqÃÃncia. O prÃ-regulador à composto por uma ponte completa de diodos em sÃrie com um conversor boost. A motivaÃÃo para este estudo consiste em avaliar os benefÃcios da utilizaÃÃo de inversores multinÃveis em baixas potÃncias (<10kVA) em UPS, com Ãnfase nos rendimentos das topologias. A utilizaÃÃo do inversor multinÃvel operando em baixa freqÃÃncia garante menores Ãndices de EMI, menores esforÃos de tensÃo e corrente nos semicondutores da estrutura, desprezÃveis perdas por comutaÃÃo e consequentemente maior rendimento. A estrutura utilizada possui ainda a caracterÃstica de garantir isolamento galvÃnico da rede elÃtrica com a carga atravÃs da utilizaÃÃo do transformador intrÃnseco desta topologia. O prÃregulador possui uma topologia que garante facilidade de implementaÃÃo e alto rendimento. O modo rede de um sistema ininterrupto de energia de 3kVA com tensÃo de entrada e saÃda de 220V e 60Hz, foi implementado. As simulaÃÃes e os resultados experimentais para um protÃtipo monofÃsico sÃo apresentados para a validaÃÃo da estrutura. O rendimento mÃximo obtido para o protÃtipo foi de 90%.

CoordenaÃÃo de AperfeÃoamento de Pessoal de NÃvel Superior / "Este trabalho apresenta um estudo dos inversores multinÃveis em cascata usando cÃlulas H-bridge na configuraÃÃo assimÃtrica usando transformador de mÃltiplos secundÃrios. Ele demonstra equaÃÃes para o cÃlculo da freqÃÃncia das cÃlulas para o inversor operando com as configuraÃÃes binÃria e ternÃria, bem como o projeto completo do transformador toroidal com nÃcleo laminado. Este trabalho define a melhor freqÃÃncia de operaÃÃo do transformador que possibilita reduÃÃo no tamanho se comparado a operaÃÃo em 60 Hz. Ele tambÃm aborda uma metodologia para o cÃlculo das perdas nas cÃlulas do inversor as quais sÃo Ãteis para o cÃlculo tÃrmico do inversor." / This dissertation proposes a design of a cascaded multilevel inverter using H-bridge cells in asymmetric configuration and a multiple secondary transformer. Equations for determining the frequency operation of each cell with binary and ternary configurations, as well as the complete design of toroidal transformer with laminated core. This work proposes also the optimal operating frequency of the transformer that enables reduction in core size, when compared to 60 Hz operation. It is also discussed a methodology for calculate the losses in the cells of the inverter, which are useful to determine the thermal behavior of the inverter.

Multilevel inverters have advantages over two-level inverters such as reduced THD, ability to operate at low switching frequencies, reduced switching losses etc. Moreover, higher voltage levels can be handled with devices of lower voltage rating. The main disadvantage with the multilevel configurations compared to the two-level inverter configuration is the increase in the number of power devices required and the circuit complexity, which necessitates complex control schemes that add to the cost. Also, the reliability of the converters comes down as the number of devices increases. Reduction in complexity and modularity are desirable characteristics for the multilevel inverters. Open-end winding Induction Motor (IM) drive configurations are shown to have advantages over the motor drive schemes with isolated neutral. The DC-link requirement in case of open-end winding structures comes down to half the voltage rating of the conventional NPC inverters. The DC- link requirement in case of open-end winding structures comes down to half compared to that of the conventional NPC inverters. The number of switching states is higher in the case of open-end winding configuration compared to multiplicity of switching states of conventional NPC inverters, which gives a control flexibility that can be used for optimizing the hardware requirements. Taking advantage of the flexibility given by open-end winding configuration, this thesis proposes schemes which have reduced power circuit complexity. Non-sinusoidal voltage fed IM drives suffer from the problems related to the common mode voltage (CMV) generated by the inverters. This CMV causes bearing currents and shaft voltages which in turn cause increased conducted EMI, ground loop currents and premature bearing failure. A three-level scheme was proposed for an open-end winding Induction machine in the literature, which completely eliminate the CMV variation from the pole voltages as well as the phase voltages. This configuration uses 24 controlled switches and two isolated DC-sources. In this thesis, three-level inverter schemes with CMV elimination and reduced power device count for an open-end winding IM drive are proposed. The first scheme gets the reduction in switch count by sharing the top inverter of the three-level scheme and the second scheme achieves the same by sharing the bottom inverter. This way, the number of controlled switches comes down to 18 from 24. Another problem with multilevel inverters is the large number of isolated DC-sources required to achieve the multilevel inversion. Reducing the number of isolated supplies and using capacitors to split the voltage levels poses the problem of capacitor voltage balancing. A four-level inverter with both CMV elimination and capacitor voltage balancing for an open-end winding IM drive is proposed in this thesis. The motor is fed by two four-level inverters from both the sides. A closed loop capacitor voltage balancing scheme is implemented and the redundancies in the switching states are used for achieving the capacitor voltage balancing and thereby reducing the total number of DC-link to two. The control scheme is independent of the load power factor and maintains the balance in the entire modulation range. A five-level inverter scheme is proposed for an open-end winding IM drive in this thesis. It requires only two isolated DC-sources to achieve the five-level inversion. The motor is fed by one NPC three-level inverter from one side and a two-level inverter from the other. The inverters on either side share the DC-sources. Common mode voltage in the phases are made zero in an average sense using sine-triangle modulation in the proposed scheme so that the common mode currents through the phases are suppressed. The maximum fundamental voltage that can be obtained at the phase is limited to 0.5Vdc. DC-link requirement of the inverter scheme is half of that of conventional five-level inverter scheme because of the open-end winding structure. The two-level inverter, which should withstand half the DC-link voltage, is always in square wave operation and hence the switching losses are very less. All the schemes are simulated extensively in MATLAB/Simulink and experimentally verified on laboratory prototypes under V/f control. TI Motor control DSP and Xilinx CPLD/FPGA are used for generation of the PWM signals for the schemes. The inverters are switched at around 1.25 kHz to keep the switching losses low. Due to laboratory constraints, the experimental verification is done on low power prototypes. Nonetheless, the generality of the schemes allow them to be used for medium voltage high power applications.

No description available.

This thesis investigates a novel DC/AC resonant inverter of Induction Heating (IH) system presenting a Multilevel Neutral Point Clamped (MNPCI) topology, as a new part of power supply design. The main function of the prototype is to provide a maximum and steady state power transfer from converter to the resonant load tank, by achieving zero current switching (ZCS) with selecting the best design of load tank topology, and utilizing the advantage aspects of both the Voltage Fed Inverter (VFI) and Current Fed Inverter (CFI) kinds, therefore it can considered as a hybrid-inverter (HVCFI) category . The new design benefits from series resonant inverter design through using two bulk voltage source capacitors to feed a constant voltage delivery to the MNPCI inverter with half the DC rail voltage to decrease the switching losses and mitigate the over voltage surge occurred in inverter switches during operation which may cause damage when dealing with high power systems. Besides, the design profits from the resonant load topology of parallel resonant inverter, through using the LLC resonant load tank. The design gives the advantage of having an output current gain value of about Quality Factor (Q) times the inverter current and absorbs the parasitic components. On the contrary, decreasing inverter current means decreasing the switching frequency and thus, decreasing the switching losses of the system. This aspect increases the output power, which increases the heating efficiency. In order for the proposed system to be more reliable and matches the characteristics of IH process , the prototype is modelled with a variable LLC topology instead of fixed load parameters with achieving soft switching mode of ZCS and zero voltage switching (ZVS) at all load conditions and a tiny phase shift angle between output current and voltage, which might be neglected. To achieve the goal of reducing harmonic distortion, a new harmonic control modulation is introduced, by controlling the ON switching time to obtain minimum Total Harmonic Distortion (THD) content accompanied with optimum power for heating energy.