CoordenaÃÃo de AperfeiÃoamento de Pessoal de NÃvel Superior / Visando superar os desafios inerentes à conversÃo de energia elÃtrica em sistemas de alta potÃncia, minimizando as perdas e melhorando a qualidade da energia processada, este tra-balho tem por objetivo analisar e implementar uma tÃcnica de modulaÃÃo para ser aplicada nas duas topologias de inversores multinÃveis mais disseminadas - com neutro grampeado (NPC), e com capacitor flutuante (FC) - a fim de reduzir os esforÃos nos semicondutores, bem como melhorar o Ãndice de distorÃÃo harmÃnica da tensÃo de saÃda. Ao longo do trabalho foi evidenciada a necessidade da digitalizaÃÃo da tÃcnica proposta, visto que o desenvolvimento analÃgico da mesma acarretaria em um circuito complexo e de baixa confiabilidade. Dessa forma, escolheu-se como plataforma digital um FPGA, devido à sua facilidade de programa-ÃÃo e reconfiguraÃÃo, alÃm da alta velocidade e quantidade de pinos de entrada e saÃda. AlÃm da tÃcnica proposta, foram tambÃm desenvolvidas outras modulaÃÃes para fins de compara-ÃÃo, apresentando os padrÃes de chaveamento para cada uma delas, bem como o comporta-mento da corrente atravÃs dos semicondutores em cada perÃodo de chaveamento. Foi tambÃm realizada a anÃlise teÃrica das topologias e suas respectivas etapas de operaÃÃo, caracterÃsticas e levantamento das equaÃÃes que ditam a anÃlise das perdas para as diferentes situaÃÃes de tÃcnicas aplicadas a cada uma das estruturas. O desenvolvimento digital das tÃcnicas mostrou-se correta atravÃs da anÃlise das formas-de-onda colhidas por meio de um circuito digital-analÃgico. AlÃm disso, a comparaÃÃo da aplicaÃÃo dessas modulaÃÃes em inversores a trÃs nÃveis NPC e FC de 6 kW mostrou-se favorÃvel à tÃcnica proposta em termos de eficiÃncia e reduÃÃo da distorÃÃo harmÃnica em ambas as topologias, comprovando sua utilidade em con-versores multinÃveis de alta potÃncia. Por fim, foi apresentado o desenvolvimento da tÃcnica proposta em inversores com mais de trÃs nÃveis, onde se pode comprovar sua eficiente aplica-ÃÃo para tais fins, bem como sua expansibilidade para inversores de n nÃveis. / In order to overcome the challenge of processing electric energy in high power systems with minimal losses and high energy quality, this work presents the implementation and anal-ysis of a modulation technique applicable on both most well-known multilevel inverter struc-tures - neutral point-clamped (NPC), and flying capacitors (FC) - to reduce the stresses across the semiconductors devices, and to improve the total harmonic distortion of the output volt-age. Throughout the work, the necessity to digitalize the proposed technique has been evi-denced due to the high complexity and low reliability inherent to the analogical approach. Thus, the digital controller FPGA has been chosen, as it is easy to program and reconfigure, works at high speed, and has a lot of input and output pins. Additionally, other modulation techniques were also implemented to compare their performance with the proposed one, pre-senting the switching patterns and the behavior of the electrical currents through the semicon-ductors for each modulation. A theoretical analysis was also performed for both topologies and their respective operation principle, characteristics, and equations used on the losses anal-ysis for the different combinations of modulation applied to each structure. Finally, the digital development of the various techniques has proved to be correct by observing the waveforms obtained through the digital/analogical circuit. Besides, the comparison of the modulation techniques on 6 kW NPC and FC three-level prototype inverters proved to be favorable to the proposed technique in terms of efficiency and total harmonic distortion reduction on both topologies, confirming its usefulness on high power multilevel converters. At last, it was pre-sented the application of the proposed modulation technique to inverters with more than three levels, where it was observed its eligibility for n-levels topologies.

Use of multilevel inverters are inevitable in medium and high voltage drives. This is due to the fact that the multilevel inverters can produce voltages in smaller steps which will reduce the harmonic content and result in more sinusoidal voltages and currents as compared to voltages and currents from two-level inverters. Due to the device limitations, use of two-level inverters is not possible in medium and high voltage drive applications. Though multiple devices can be connected both in series and parallel to achieve two-level operation, the output voltages still suffer from high harmonic content. Multilevel inverters have multiple DC voltage levels with switches that enable one of the voltage steps to be applied to the load. Due to decrease in step size during each switching instant, output voltages and currents of the multilevel inverters have considerably less harmonic content. As the number of levels increase, the switching step reduces thereby the harmonic content also reduces drastically. Due to their advantages, multilevel inverters have gained lot of acceptance in the industry even at lower voltages. The three main configurations that have gained popularity are the neutral point clamped converter, the flying capacitor converter and the cascaded H-bridge converter. Each converter has its own set of advantages and disadvantages. Based on the requirements of various applications, it is possible to fabricate hybrid multilevel topologies that are combinations of the three basic topologies. Researchers around the world have proposed several such converters for diverse applications so as to suit particular requirements like modularity, ease of control, improved reliability, fault tolerant capability etc. The present thesis explores multilevel converters with single DC link to be used for motor drive and grid connected applications. A novel five-level inverter topology formed by cascading a floating capacitor H-bridge module to a regular three-level flying capacitor inverter has been explored in chapter 2. The three-level flying capacitor inverter can generate pole voltages of 0, VDC /2 and VDC . By cascading it with another floating capacitor H-bridge of voltage magnitude VDC /4, pole voltages of 0, VDC /4, VDC/2, 3VDC /4 and VDC . Each of these pole voltage levels can have one or more switching combinations. However each switching combination has a unique effect on the state of the two capacitor voltages. By switching through redundant switching combinations for the same pole voltage, the two capacitors present in each phase can be balanced. The proposed topology also has an advantage that if one of the devices in the H-bridge fails, the topology can still be operated as a regular three-level flying capacitor inverter that can supply full load at rated power by bypassing the faulty H-bridge. This fault tolerant operation of the converter will enable it to be used in applications like traction and marine drives where high reliability is needed. The proposed converter needs a single DC link. All the required voltage levels can be generated from the single DC link. This enables back to back grid connected operation possible where multiple converters can interact with a single DC link. Various pole voltage switching combination and its effect on individual capacitor has been studied. A control algorithm to balance the capacitor voltages by switching through multiple redundancies for the same pole voltage has been developed. The proposed configuration has been implemented in hardware using IGBT H-bridge modules and the control circuitry is realized using DSP and FPGA. The performance of the drive is verified for various frequencies and modulation indices during steady state by running a three phase induction motor at no load. The stability of the drive during transients has been studied by accelerating the machine suddenly at no load and analyzing the performance of the drive. The capacitor voltages are made to deviate from their intended values and the capacitor balancing algorithm has been verified for its ability to bring the capacitor voltages back to their intended values. The experimental results have been presented and discussed in detail in the chapter 2. In the third chapter a common-mode voltage eliminated three-level inverter using a single DC link has been proposed. The power schematic is similar to the one presented in chapter 2. In this chapter the space vector polygon formed by the three phases of the proposed topology has been presented. The common-mode voltage generated by different pole voltage combinations for same space vector location and the redundant switching state combinations has been studied. The pole voltage combinations with zero common mode voltage have been studied. The switching state redundancies for the the pole voltage have been studied. The space vector polygon formed with the pole voltage combinations has been analyzed. A drive is made with the proposed common-mode voltage eliminated inverter. The performance of the drive is tested for various modulation indices and frequencies by running a three phase squirrel cage induction motor at no load. The transient performance is verified by accelerating the motor suddenly and checking the common-mode voltage along with the capacitor voltages. The results have been presented and discussed in detail in chapter 3. This converter has advantages like use of single DC supply, ability to operate as a regular three level converter in case of failure of one of the H-bridges. The work presented in fourth chapter proposes a novel three phase 17-level inverter configuration which utilizes a single DC supply. The rest of voltages are generated using three floating capacitor H-bridges. The redundant switching combinations for generating various pole voltages and their effect on the capacitors have been studied and suitable capacitor balancing algorithm has been developed. The proposed topology has been realized in hardware and the performance of the drive during steady state has been studied by running an induction motor at various modulation indices and frequencies. The transient response of the drive has been observed by accelerating the motor suddenly under no load. The results have been presented in detail in chapter four. This configuration also needs a single DC link. The advantages of this configuration is in case of failure of any devices in the H-bridge, the drive can be operated at reduced number of levels while supplying full load current. This feature helps the drive to be used in fault tolerant applications like marine and traction drives where reliability of the drive is of prime importance. All the topologies that have been presented in the previous chapters have mentioned about the usage of the proposed genre of topologies use single DC link and hence will enable back to back grid tied inverter connection. In the fifth chapter this has has been verified experimentally. The three phase squirrel cage induction motor is driven by using the seventeen-level inverter drive proposed in chapter four. A five-level active front-end is realized by the converter topology proposed in chapter two. The converter is run and the performance of the drive is studied at various modulation indices and speeds of the motor. Various aspects like re-generation operation, acceleration and other aspects of the drive have been studied experimentally and the results are presented in detail. For experimental setup, Semikron SKM75GB12T4 IGBT modules have been used to realize the power topology. These IGBTs are driven by M56972L drivers. The control circuit is realized using TMS320F2812 DSP along with Xilinx Spartan 3 FPGA (XC3S200) has been used. The voltages and currents are sensed using LEM LV-20P and LA 55-P hall effect based sensors.