Cascaded H-bridge (CHB) multilevel inverters have significant popularity with motor drives applications due to their modularity, scalability, and reliability. Typical CHB inverters employ diode rectifiers that allow unidirectional power flow from the grid to the load. To capture and utilize the regenerated energy in regenerative applications, regenerative CHB drives were introduced with two-level voltage source converters in the front end to allow bidirectional energy flow. This solution is accompanied by challenges of high number of switches and control circuits, high switching power losses, and massive dimensions. Recently, developing more economic versions of regenerative cascaded H-bridge drives has become one of the hottest topics in power electronics research. In this thesis work, two solutions are proposed for more energy efficient and economic regenerative CHB drives. The first solution is a proposed power cell configuration that reduces the number of switches per cell by two. Additionally, phase alternation connection method and carrier phase-shifting techniques are introduced to address the challenges of the presented configuration. The switch-count reduction reduces the system’s complexity, switches’ cost, and footprint. The second proposed solution is a new controller to operate the front-end converters as fundamental frequency ends (FFEs). The proposed controller is employed in both the conventional regenerative cascaded H-bridge and the proposed reduced switch-count configuration. This solution minimizes the switching power losses, and results in more compact and economic design, with higher DC-link utilization. Theoretical analysis and simulation studies of both proposed solutions show promising performance and capability to be applied as energy-efficient and cost effective regenerative CHB motor drives. Experimental validation of the proposed reduced switch-count configuration is presented for STATCOM operation of a scaled-down 7-Level regenerative CHB drive system. The future work of this thesis includes experimental validation of the proposed FFE controller, and operation of the system with regenerative motor load. / Thesis / Master of Applied Science (MASc)

High power converters are widely used in many industries. At power levels in the range of Mega Watt (MW), power conversion at medium voltage (MV) is preferred due to better efficiency and lower cost. For medium voltages applications, multilevel converters are widely adopted due to the features they offer with respect to two-level converters. Cascaded H-bridge topology is a widely adopted multilevel topology because of its modularity, scalability, and reliability. The conventional cascaded H-bridge topology allows two-quadrant operation. In order to allow fourquadrant operation, an active front end version of the cascaded H-bridge topology has been proposed in literature and recently commercialized. In the field, power converters operates under harsh loading and environmental conditions. The resulting stresses imposed on converter components cause their gradual degradation. In cascaded H-bridge converters, typically power cell components such as power modules, DC-bus capacitors, and control PCBs are v highly stressed. Under these stresses power cell components degrade and require replacement in the field, otherwise unexpected failures may occur. The thesis aim is to address power cell components reliability through proposing novel regenerative cascaded H-bridge converter control schemes to reduce components stresses and failure probability without increasing size, cost, or complexity. First, a novel PWM active front end control scheme has been proposed to reduce the inherent ripple current stresses on the DC-bus capacitors. Second, the thesis proposes a novel grid or near grid switching frequency front end control scheme to reduce stresses on power modules and the power cell cooling requirements. Third, novel cascaded H-bridge front end control schemes are proposed to reduce the sensor count, thereby decreasing failure rate and cutting down cost. The proposed work has been thoroughly validated through detailed 9- cell regenerative cascaded H-bridge system simulation and experimentation. / Thesis / Doctor of Philosophy (PhD)

In high-power electric drives, multilevel inverters are generally deployed to address issues such as electromagnetic interference, switch voltage stress and harmonic distortion. The switching frequency of the inverter is always kept low, of the order of 1KHz or even less to reduce switching losses and synchronous pulse width modulation (PWM) is used to avoid the problem of sub-harmonics and beat frequencies. This is particularly important if the switching frequency is very low. The synchronous PWM is getting popularity as its realization is very easy with digital controllers compared to analog controllers. Neutral-point-clamped (NPC) inverters, cascaded H-bridge, and flying-capacitor multilevel inverters are some of the popular schemes used for high-power applications. Hybrids of these multilevel inverters have also been proposed recently to take advantage of the basic configurations. Multilevel inverters can also be realized by feeding the induction motor from both ends (open-end winding) using conventional inverter structures. For controlling the output voltage of these inverters, various PWM techniques are used. Chapter-1 of this thesis provides an over view of the various multilevel inverter schemes preceded by a discussion on basic two-level VSI topology. The inverters used in motor drive applications have to be operated in over-modulation range in order to extract the maximum fundamental output voltage that is possible from the dc-link. Operation in this high modulation range is required to meet temporary overloads or to have maximum power operation in the high speed range (flux weakened region). This, however, introduces a substantial amount of low order harmonics in the Motor phase voltages. Due to these low-order harmonic frequencies, the dynamic performance of the drive is lost and the current control schemes are severely affected especially due to 5th and 7th harmonic components. Further, due to these low-order harmonics and non-linear PWM operation in over-modulation region, frequent over-current fault conditions occur and reliability of the drive is jeopardized. The twelve sided-polygonal space vector diagram (dodecagonal space vectors) can be used to overcome the problem of low order 5th and 7th harmonics and to give more range for linear modulation while keeping the switching frequency at a minimum compared to conventional hexagonal space vector based inverters. Thus, the dodecagonal space-vector switching can be viewed as an engineering compromise between low switching frequency and quality load current waveform. Most of the previous works of dodecagonal space-vector generation schemes are based on NPC inverters. However, sophisticated charge control schemes are required in NPC inverters to deal with the neutral-point voltage fluctuation and the neutral-point voltage shifting issues. The losses in the clamping diodes are another major concern. In the second chapter, a multilevel dodecagonal space-vector generation scheme based on flying capacitor topology, utilizing an open end winding induction motor is presented. The neutral point charge-balancing problem reported in the previous works is not present in this scheme, the clamping diodes are eliminated and the number of power supplies required has been reduced. The capacitors have inherent charge balancing capability, and the charge control is done once in every switching cycle, which gives tight voltage control for the capacitors. For the speed control of induction motors, the space-vector PWM scheme is more advantageous than the sine-triangle PWM as it gives a more linear range of operation and improved harmonic performance. One major disadvantage with the conventional space-vector PWM is that the trigonometric operations demand formidable computational efforts and look-up tables. Carrier based, common-mode injected PWM schemes have been proposed to simplify the PWM process. However, the freedom of selecting the PWM switching sequences is limited here. Another way of obtaining SVPWM is using the reference voltage samples and the nearest vector information to switch appropriate devices for proper time intervals, realizing the reference vector in an average sense. In-formation regarding the sector and nearest vectors can be easily obtained by comparing the instantaneous amplitudes of the reference voltages. This PWM approach is pro-posed for the speed control of the motor in this thesis. The trigonometric operations and the requirement of large look-up tables in the conventional SVPWM are avoided in this method. It has the additional advantage that the switching sequences can be decided at will, which is helpful in reducing further, the harmonic distortion in certain frequency ranges. In this way, this method tries to combine the advantages of vector based methods (conventional SVPWM) and scalar methods (carrier-based methods). The open-end winding schemes allowed the required phase voltage levels to be generated quite easily by feeding from both ends of the windings. Thus, most of the multilevel inverters based on dodecagonal space-vector structures relied on induction motors with open-end windings. The main disadvantage of open-end winding induction motor is that six wires are to be run from the inverter to the motor, which may be unacceptable in certain applications. Apart from the inconvenience of laying six wires, the voltage reflections in the wires can lead to over voltages at the motor terminals, causing insulation failures. Where as the topology presented in chapter-2 of this thesis uses open-end winding motor with flying-capacitor inverters for the generation of dodecagonal space-vectors, the topology presented in chapter-3 utilizes a cascade connection of flying-capacitors and floating H-bridge cells to generate the same set of voltage space-vectors, thus allowing any standard induction motor as the load. Of the methods used for the speed control of induction motors, namely sine-triangle PWM and space vector PWM, the latter that provides extra modulation range is naturally preferred. It is a well-understood fact that the way in which the PWM switching sequences are applied has a significant influence on the harmonic performance of the drive. However, this topic has not been addressed properly for dodecagonal voltage space-vector based multilevel inverter drives. In chapter-4 of the thesis, this aspect is taken into ac-count and the notion of “harmonic flux trajectories” and “stator flux ripple” are used to analyze the harmonic performance of the various PWM switching schemes. Although the PWM method used in this study is similar to that in chapter-2, the modification in the PWM switching sequence in the PWM algorithm yields significant improvements in harmonic performance. The proposed topologies and PWM schemes are extensively simulated and experimentally verified. The control scheme was implemented using a DSP processor running at a clock frequency 150MHz and a four-pole, 3.7kW, 50Hz, 415V three-phase induction motor was used as the load. Since the PWM ports are limited in a DSP, a field-programmable gate array (FPGA) was used to decode the PWM signals from the DSP to generate timing information required for PWM sequencing for all the power devices. The same FPGA was used to generate the dead-time signals for the power devices also.