Among PWM power conversion topologies, the single-switch forward topology is the one that has been most widely used for decades. Its popularity has been based on many factors, including its low cost, circuit simplicity and high efficiency. However, several issues need to be addressed when using the forward converter such as the core reset, the voltage spikes caused by the transformer leakage inductance, and the pulsating input current waveform. The transformer is driven in a unidirectional fashion in the forward converter; a tertiary forward converter (TFC) is an example of this. Therefore, the third winding and reset diode must be provided with an adequate period of reset time so that the flux can be fully reset by the end of each switching cycle to prevent core saturation. Also, due to the utilization of a transformer, leakage inductances cannot be avoided. The energy stored in the leakage inductance during current ramp-up is not transferred to the load, and is not recovered during its discharge phase. As a result, the VDS waveform has a voltage spike and undesirable high-frequency oscillation. Therefore, a higher voltage-rating switch should be used to reduce the risk of high-voltage breakdown. Although a switch with amply high voltage ratings is available, it would tend to have a higher on-resistance, RDS(ON), resulting in increased conduction losses. Moreover, selection of a switch with higher voltage ratings than necessary may needlessly increase the cost of the design. Usually an additional circuit such as a snubber circuit or a clamp circuit or the soft-switching technique is used to absorb these voltage spikes. Consequently, the leakage inductance is intentionally minimized in the PWM power conversion technique so that it will not degrade the circuit performance. In contrast, the leakage inductance of the transformer may enhance rather than detract from circuit performance with a resonant power conversion technique. To date, however, no single-switch forward converter has been claimed to be able to enhance the converter performance with the PWM power conversion technique by utilizing the leakage inductance. Therefore, research on the utilization of the transformer leakage inductance in the PWM forward converter is needed. Two techniques, input current ripple reduction and an embedded filter, are proposed to enhance the performance of forward converter using the PWM technique. By inserting a capacitor between two primary windings of the TFC, an input current ripple reduction technique is proposed and a forward converter with ripple reduction (FRR) is presented in this research work. Because the voltage of the capacitor is clamped to input voltage, the capacitor becomes a second voltage source to share part of the load current. As a result, the input current ripple is reduced. Moreover, the capacitor voltage is clamped both at the static and dynamic states; thus the excessive voltage stress on the main switch S1 of the FAC during low-line to high-line step transient is eliminated. Furthermore, without an external LC filter, the EMI noise levels can be further reduced as a result of the embedded notch filter formed by the transformer leakage inductance and clamp capacitor if the notch frequency is designed to be the same as the switching frequency. With the help of the clamp capacitor, therefore, the leakage inductance can enhance rather than detract from the converter performance. The input current ripple can be reduced further by employing the proposed techniques. Two sets of the clamp capacitors and the leakage inductances are utilized, and the current ripple can even be cancelled if the condition is met. Consequently, the input current becomes a non-pulsating waveform and a forward converter with ripple cancellation (FRC) is presented. Moreover, without an external LC filter, the EMI noise levels can be further attenuated as a result of the embedded low-pass filter formed by the transformer leakage inductances and clamp capacitors. Again, the leakage inductance can enhance the converter performance just as the resonant converter does. In addition to providing the analysis and design procedure, this work verifies the performance of the presented converters, the FRR and the FRC, by the experimental results. By employing the proposed techniques, eight new topologies have been extended for different power conversion applications. Each member of the FRR and the FRC families is able to enhance the converter performance, in ways such as the elimination of the voltage spikes on the main switch without a snubber circuit and the improvement of the EMI performance with small filter components. Consequently, the cost can be reduced and the space of the converter can be saved. / Ph. D.

This thesis presents the simulation, design, and hardware implementation of a modified multiphase boost converter. Converter design must consider noise imposed on input and output nodes which connect to and influence the operation of other devices. Excessive noise introduces EMI which can damage sensitive circuits or impede their operation. High ripple current degrades battery lifetime and reduces operating efficiency in connected systems such as PV arrays. Converters with high ripple current also experience greater peak conduction loss and require larger components. A two-phase implementation of a modified boost converter demonstrates the input current filtering benefits of the modified topology with increased power capacity. In a 12V to 19V 95W design, the modified multiphase design exhibits a reduced input current ripple of 1.103% compared to the 9.096% of the standard multiphase design while imposing minimal detriment to overall converter efficiency. The modified topology uses two inductors and one feedback capacitance per phase. Larger value inductors generally exhibit lower current ratings as well as larger size. The split inductance of the modified multiphase topology can be designed for occupation of less total volume than the single inductance of the standard multiphase topology.

With solar power and other renewables set to take over the market in the coming decades, maximum power point tracking will be essential to optimizing power output. One underserved topic of research is the effect of inductor current ripple on performance of Maximum Power Point Tracking (MPPT) algorithms. Many new topologies are focused on decreasing the ripple from PV source to increase efficiency and power output. However, not much has been done to show ripple degrading performance of MPPT algorithms. This study uses a boost converter topology to test the performance of constant duty cycle step Perturb and Observe (PO), Incremental Conductance IC, and Constant Voltage (CV) PID over a range of inductor current ripple factor. Inductor current ripple is controlled solely by changing inductance. This study concluded that all three algorithms were quite robust and affected very little over an inductor current ripple factor range of 20% to 40%. One novel finding was increased duty cycle oscillation when the MPPT update and sample speed was faster than the boost converter response.

The delivery of high power and smaller footprints through a non-isolated topology demands for the use of multiphase topology in DC-DC converters. Multiphase reduces the ripple observed on both the input and output waveforms; however, it may not be enough to connect to sensitive power sources such as renewable energy sources. A single-phase modified boost converter demonstrates the ability to acquire very minimal input current ripple by addition of passive components. The expansion to multiphase topology is the next logical step for higher power application while furthering the low input current ripple benefit. In this thesis, the multiphase modified boost topology is compared with the multiphase standard boost topology to explore the benefits and trade-offs of the proposed topology. A 12V input to 19V output at 95W output power multiphase standard and modified boost converters were designed and constructed for the thesis. Results from theoretical calculations, computer simulations, and hardware implementations were then compared to evaluate their performances. Results show that compared to the standard boost, the modified boost yields significantly less input current ripple at 2% under full load condition while maintaining output voltage ripple of 5% and higher than 90% efficiency.

Doubly-Salient Reluctance Machines (DSRMs) sidestep many of the issues with permanent magnet and induction machines and embody the lowest cost and simplest manufacturing of the motor technologies. Major drawbacks to RMs have been (1) the need for failure-prone electrolytic capacitors, (2) large torque ripple, and (3) acoustic noise. Conventionally, these drawbacks have been addressed independently either through (1) excitation control or (2) machine design, but not as a holistic system or solution. This disseratation presents a design for high-efficiency low-cost RM while producing smooth output torque and avoiding pulsating inverter input current and the associated electrolytic capacitor. We propose a method for shaping the machine reluctance profile to reduce machine torque ripple to a desired level (here, <5%) without compromising on machine efficiency or power density, a Shaped Reluctance Machine (ShRM). Furthermore, a comprehensive approach which combines both phase excitation control and machine design to cooperatively address the excursions of input and output powers from their average values which results in less than 5% ripple for both electrical and mechanical net power — essentially a DC Reluctance Machine (DCRM). Compared to conventional practice in DSRMs, electrical power ripple is reduced by 85 times and torque ripple is reduced by almost 20 times, while overall efficiency, torque density, and power density are maintained. / Ph. D.

Submitted by PPG Engenharia El?trica (engenharia.pg.eletrica@pucrs.br) on 2018-10-31T13:57:50Z No. of bitstreams: 1 SILVIO CESAR ANTUNES DUTRA_DIS.pdf: 2550584 bytes, checksum: 3dae5cef4ef20b66d5c7a4db79ae5cad (MD5) / Approved for entry into archive by Sheila Dias (sheila.dias@pucrs.br) on 2018-11-01T11:50:43Z (GMT) No. of bitstreams: 1 SILVIO CESAR ANTUNES DUTRA_DIS.pdf: 2550584 bytes, checksum: 3dae5cef4ef20b66d5c7a4db79ae5cad (MD5) / Made available in DSpace on 2018-11-01T12:00:28Z (GMT). No. of bitstreams: 1 SILVIO CESAR ANTUNES DUTRA_DIS.pdf: 2550584 bytes, checksum: 3dae5cef4ef20b66d5c7a4db79ae5cad (MD5) Previous issue date: 2018-08-31 / Power converters are widely used in the context of power electronics. In the same way that transformers have a fundamental role in applications involving AC circuits, power converters modify voltage magnitudes in DC circuits. These devices can either present an output voltage higher than the input voltage, acting as a Boost converter, or lower, acting, in this case, as a Buck converter. The input and output signals can also present either a voltage source or a current source behavior, depending on the topology. This work presents a systematic study of the D converter operating in the continuous conduction mode, in permanent regime, including the qualitative and quantitative analyzes, resulting in a methodology of dimensioning of the converter, as well as its modeling in space of states, which makes feasible studies of control strategies for it. Although this is not a new topology, this converter has recently been reintroduced due to its ability to increase efficiency in the energy conversion process, especially in photovoltaic systems. However, this research is fully justified given the lack of similar work for the D converter topology. This study was validated from tests performed in the PSIM simulation software, in addition to MATLAB / SIMULINK. A laboratory prototype was specially constructed for validation purposes in a rapid prototyping platform, as well as the consequent implementation in a PCI, for use in future works. / Os conversores est?ticos s?o amplamente utilizados no contexto da eletr?nica de pot?ncia. Da mesma forma que os transformadores t?m papel fundamental nas aplica??es que envolvem circuitos alimentados em corrente alternada, os conversores est?ticos realizam a transforma??o de magnitudes de tens?o em circuitos de corrente cont?nua. Tais dispositivos podem tanto apresentar em sua sa?da um valor de tens?o superior em rela??o ao sinal de entrada, atuando como elevadores, quanto inferior, atuando, neste caso, como redutores. Estes tamb?m podem apresentar suas sa?das ou entradas com um comportamento de fonte de tens?o ou corrente, dependendo da topologia utilizada. Este trabalho apresenta um estudo sistematizado do conversor D operando no modo de condu??o cont?nua, em regime permanente, incluindo as an?lises qualitativa e quantitativa, resultando em uma metodologia de dimensionamento do conversor, bem como a sua modelagem em espa?o de estados, o que viabiliza estudos de estrat?gias de controle para o mesmo. Apesar de n?o se tratar de uma nova topologia, recentemente este conversor foi reintroduzido, devido a sua capacidade de aumentar a efici?ncia no processo de convers?o de energia, especialmente em sistemas fotovoltaicos. Esta pesquisa encontra justificativa dada a inexist?ncia de trabalhos semelhantes especificamente para a topologia do conversor D. Este estudo foi validado a partir de ensaios realizados no software de simula??o PSIM, al?m do MATLAB/SIMULINK. Um prot?tipo de laborat?rio foi especialmente constru?do para fins de valida??o em uma plataforma de prototipagem r?pida, bem como a consequente implementa??o do mesmo em uma PCI, para utiliza??o em trabalhos futuros.

No description available.

Voltage source inverter (VSI) is used to control the speed of an induction motor by applying AC voltage of variable amplitude and frequency. The semiconductor switches in a VSI are turned on and off in an appropriate fashion to vary the output voltage of the VSI. Various pulse width modulation (PWM) methods are available to generate the gating signals for the switches. The process of PWM ensures proper fundamental voltage, but introduces harmonics at the output of the VSI. Ripple in the developed torque of the induction motor, also known as pulsating torque, is a prominent consequence of the harmonic content. The harmonic voltages, impressed by the VSI on the motor, differ from one PWM method to another. Space-vector-based approach to PWM facilitates a large number of switching patterns or switching sequences to operate the switches in a VSI. The switching sequences can be classified as conventional, bus-clamping and advanced bus-clamping sequences. The conventional sequence switches each phase once in a half-carrier cycle or sub-cycle, as in case of sine-triangle PWM, third harmonic injection PWM and conventional space vector PWM (CSVPWM). The bus-clamping sequences clamp a phase to one of the DC terminals of the VSI in certain regions of the fundamental cycle; these are employed by discontinuous PWM (DPWM) methods. Popular DPWM methods include 30 degree clamp PWM, wherein a phase is clamped during the middle 30 degree duration of each quarter cycle, and 60 degree clamp PWM which clamps a phase in the middle 60 degree duration of each half cycle. Advanced bus-clamping PWM (ABCPWM) involves switching sequences that switch a phase twice in a sub-cycle besides clamping another phase. Unlike CSVPWM and BCPWM, the PWM waveforms corresponding to ABCPWM methods cannot be generated by comparison of three modulating signals against a common carrier. The process of modulation in ABCPWM is analyzed from a per-phase perspective, and a computationally efficient methodology to realize the sequences is derived. This methodology simplifies simulation and digital implementation of ABCPWM techniques. Further, a quick-simulation tool is developed to simulate motor drives, operated with a wide range of PWM methods. This tool is used for validation of various analytical results before experimental investigations. The switching sequences differ in terms of the harmonic voltages applied on the machine. The harmonic currents and, in turn, the torque ripple are different for different switching sequences. Analytical expression for the instantaneous torque ripple is derived for the various switching sequences. These analytical expressions are used to predict the torque ripple, corresponding to different switching sequences, at various operating conditions. These are verified through numerical simulations and experiments. Further, the spectral properties are studied for the torque ripple waveforms, pertaining to conventional space vector PWM (CSVPWM), 30 degree clamp PWM, 60 degree clamp PWM and ABCPWM methods. Based on analytical, simulation and experimental results, the magnitude of the dominant torque harmonic with an ABCPWM method is shown to be significantly lower than that with CSVPWM. Also, this ABCPWM method results in lower RMS torque ripple than the BCPWM methods at any speed and CSVPWM at high speeds of the motor. Design of hybrid PWM methods to reduce the RMS torque ripple is described. A hybrid PWM method to reduce the RMS torque ripple is proposed. The proposed method results in a dominant torque harmonic of magnitude lower than those due to CSVPWM and ABCPWM. The peak-to-peak torque in each sub-cycle is analyzed for different switching sequences. Another hybrid PWM is proposed to reduce the peak-to-peak torque ripple in each sub-cycle. Both the proposed hybrid PWM methods reduce the torque ripple, without increasing the total harmonic distortion (THD) in line current, compared to CSVPWM. CSVPWM divides the zero vector time equally between the two zero states of a VSI. The zero vector time can optimally be divided to minimize the RMS torque ripple in each sub-cycle. It is shown that such an optimal division of zero vector time is the same as addition of third harmonic of magnitude 0.25 times the fundamental magnitude to the three-phase sinusoidal modulating signals. ABCPWM applies an active state twice in a sub-cycle, with the active vector time divided equally. Optimal division of active vector time in ABCPWM to minimize the RMS torque ripple is evaluated, both theoretically and experimentally. Compared to CSVPWM, this optimal PWM is shown to reduce the RMS torque ripple significantly over a wide range of speed. The various PWM schemes are implemented on ALTERA CycloneII field programmable gate array (FPGA)-based digital control platform along with sensorless vector control and torque estimation algorithms. The controller generates the gating signals for a 10kVA IGBT-based two-level VSI connected to a 5hp, 400V, 4-pole, 50Hz squirrel-cage induction motor. The induction motor is coupled to a 230V, 3kW separately-excited DC generator.

This thesis deals with analysis and implementation of Power-HIL system that is designed to simulate real DC motor with comutator and permanent magnets. For problem analysis were used simulations of real components in Matlab / Simulink. The electronic parts of system were simulated with using the SimElectronic library. Idividual hardware components were designed according to simulation results. The outcome of this thesis is a power electronic simulator of real DC motor, which is implemented on dSPACE platform. The system allows software to setup parameters and behavior of simulated motor. The final system can be used for testing DC motor ECU (electronic control units).

A voltage source inverter is commonly used to supply a variable frequency variable voltage to a three phase induction motor in a variable speed application. A suitable pulse width modulation (PWM) technique is employed to obtain the required output voltage in the line side of the inverter. Real-time methods for PWM generation can be broadly classified into triangle comparison based PWM (TCPWM) and space vector based PWM (SVPWM). In TCPWM methods such as sine-triangle PWM, three phase reference modulating signals are compared against a common triangular carrier to generate the PWM signals for the three phases. In SVPWM methods, a revolving reference voltage vector is provided as voltage reference instead of three phase modulating waves. The magnitude and frequency of the fundamental component in the line side are controlled by the magnitude and frequency, respectively, of the reference vector. The fundamental line side voltage is proportional to the reference magnitude during linear modulation. With sine-triangle PWM, the highest possible peak phase fundamental voltage is 0.5Vdc, where Vdc is the DC bus voltage, in the linear modulation zone. With techniques such as third harmonic injection PWM and space vector based PWM, the peak phase fundamental voltage can be as high as (formula) (i.e., 0:577Vdc)during linear modulation. To increase the line side voltage further, the operation of the VSI must be extended into the overmodulation region. The overmodulation region extends upto the six-step mode, which gives the highest possible ac voltage for a given (formula). In TCPWM based methods, increasing the reference magnitude beyond a certain level leads to pulse dropping, and gradually leads to six-step operation. However, in SVPWM methods, an overmodulation algorithm is required for controlling the line-side voltage during overmodulation and to achieve a smooth transition from PWM to six-step mode. Numerous overmodulation algorithms have been proposed in the literature for space vector modulated inverter. A well known algorithm among these divides the overmodulation zone into two zones, namely zone-I and zone-II. This is termed as the 'existing overmodulation algorithm' here. This algorithm is modified in the present work to reduce computational burden without much increase in the line current distortion. During overmodulation, the fundamental line side voltage and the reference magnitude are not proportional, which is undesirable from the control point of view. The present work ensures a linear relationship between the two. Apart from the fundamental component, the inverter output voltage mainly consists of harmonic components at high frequencies (around switching frequency and the integral multiples) during linear modulation. However, during overmodulation, low order harmonic components such as 5th, 7th, 11th, 13th etc., are also present in the output voltage. These low order harmonic voltages lead to low order harmonic currents in the motor. The sum of the lower order harmonic currents is termed as 'lower order current ripple'. The present thesis proposes a method for estimation of lower order current ripple in real-time. In closed loop current control, the motor current is fed back to the current controller. During overmodulation, the motor current contains low order harmonics, which appear in the current error fed to the controller. These harmonic currents are amplified by the current error amplifier deteriorating the performance of the drive. It is possible to filter the lower order harmonic currents before being fed back. However, filtering introduces delay in the current loop, and reduces the bandwidth even during linear modulation. In the present work, the estimated lower order current ripple is subtracted from the measured current before the latter is fed back to the controller. The estimation of lower order current ripple and the proposed current control are verified through simulation using MATLAB/SIMULINK and also experimentally on a laboratory prototype. The experimental setup comprises of a field programmable gate arrays (FPGA) based digital controller, an IGBT based inverter and a four-pole squirrel cage induction motor. (Pl refer the original document for formula)