Induction motor (IM) drives are employed in a wide range of industries due to low maintenance, improved efficiency and low emissions. Industrial installations of high-power IM drives rated up to 30 MW have been reported. The IM drives are also employed in ultra high-speed applications with shaft speeds as high as 500; 000 rpm. Certain applications of IM drives such as gas compressors demand high power at high speeds (e.g. 10 MW at 20; 000 rpm). In high-power voltage source inverter (VSI) fed induction motor drives, the semiconductor devices experience high switching energy losses during switching transitions. Hence, the switching frequency is kept low in such high-power drives. In high-speed drives, the maximum modulation frequency is quite high. Hence, at high speeds and/or high power levels, the ratio of switching frequency to fundamental frequency (i.e. pulse number, P ) of the motor drive is quite low. Induction motor drives, operating at low-pulse numbers, have significant low-order volt-age harmonics in the output. These low-order voltage harmonics are not filtered adequately by the motor inductance, leading to high total harmonic distortion (THD) in the line current as well as low-order harmonic torques. The low-order harmonic torques may lead to severe torsional vibrations which may eventually damage the motor shaft. This thesis addresses numerous issues related to low-pulse-number operation of VSI fed IM drives. In particular, optimal pulse width modulation (PWM) schemes for minimization of line current distortion and those for minimization of a set of low-order harmonic torques are proposed for two-level and three-level inverter fed IM drives. Analytical evaluation of current ripple and torque ripple is well established for the induction motor drives operating at high pulse numbers. However, certain important assumptions made in this regard are not valid when the pulse number is low. An analytical method is proposed here for evaluation of current ripple and torque ripple in low-pulse-number induction motor drives. The current and torque harmonic spectra can also be predicted using the proposed method. The analytical predictions of the proposed method are validated through simulations and experimental results on a 3:7-kW induction motor drive, operated at low pulse numbers. The waveform symmetries, namely, half-wave symmetry (HWS), quarter-wave symmetry (QWS) and three-phase symmetry (TPS), are usually maintained in induction motor drives, operating at low switching frequencies. Lack of HWS is well known to introduce even harmonics in the line current. Impact of three-phase symmetry on line current and torque harmonic spectra is analyzed in this thesis. When the TPS is preserved, there are no triplen frequency components in the line current and also no harmonic torques other than those of order 6, 12, 18 etc. While TPS ensures that the triplen harmonics in the three-phase pole voltages are in phase, these triplen frequency harmonics form balanced sets of three-phase voltages when TPS is not preserved. Hence, triplen frequency currents flow through the stator windings. These result in torque harmonics of order 2, 4, 6, 8, 10 etc., and not just integral multiples of 6. These findings are well supported by simulation and experimental results. One can see that two types of pole voltage waveforms are possible, when all waveform symmetries (i.e. HWS, TPS and QWS) are preserved in a two-level inverter, These are termed as type-A and type-B waveforms here. Also, QWS could be relaxed, while maintain-ing HWS and TPS, leading to yet another type of pole voltage waveform. Optimal switching angles to minimize line current THD are reported for all three types of pole voltage wave-forms. Theoretical and experimental results on a 3:7-kW IM drive show that optimal type-A PWM and optimal type-B PWM are better than each other in different ranges of modulation at any given low pulse number. In terms of current THD, the optimal PWM without QWS is found to be close to the better one between optimal type-A and optimal type-B at any modulation index for a given P . A combined optimal PWM to minimize THD is proposed, which utilizes the superior one between optimal type-A and optimal type-B at any given modulation index and pulse number. The performance of combined optimal PWM is shown to be better than those of synchronous sine-triangle (ST) PWM and selective harmonic elimination (SHE) PWM through simulations and experiments over a wide range of speed. A frequency domain (FD) based and another synchronous reference frame (SRF) based optimal PWM techniques are proposed to minimize low-order harmonic torques. The objective here is to minimize the combined value of low-order harmonic torques of order 6, 12, 18, ..., 6(N 1), where N is the number of switching angles per quarter cycle. The FD based optimal PWM is independent of load and machine parameters while the SRF based method considers both load and machine parameters. The offline calculations are much simpler in case of FD based optimal PWM than in case of SRF based optimal PWM. The performance of the two schemes are comparable and are much superior to those of synchronous ST PWM and SHE PWM in terms of low-order harmonic torques as shown by the simulation and experimental results presented over a wide range of fundamental frequency, The proposed optimal PWM methods for two level-inverter fed motor drives to minimize the line current distortion and low-order torque harmonics, are extended to neutral point clamped (NPC) three-level inverter fed drive. The proposed optimal PWM methods for the NPC inverter are compared with ST PWM and SHE PWM, having the same number of switching angles per quarter. Simulation and experimental results on a 3:7-kW induction motor drive demonstrate the superior performance of proposed optimal PWM schemes over ST PWM and SHE PWM schemes. The di_erent optimal PWM schemes proposed for two-level and three-level inverter fed drives, having di_erent objective functions and constraints, are all analyzed from a space vector perspective. The three-phase PWM waveforms are seen as a sequence of voltage vector applied in each case. The space vector analysis leads to determination of optimal vector sequences, fast o_ine calculation of optimal switching angles and e_cient digital implementation of the proposed optimal PWM schemes. A hybrid PWM scheme is proposed for two-level inverter fed IM drive, having a maximum switching frequency of 250 Hz. The proposed hybrid PWM utilizes ST PWM at a _xed frequency of 250 Hz at low speeds. This method employs the optimal vector sequence to minimize the current THD at any speed in the medium and high speed ranges. The proposed method is shown to reduce both THD as well as machine losses signi_cantly, over a wide range of speed, compared to ST PWM Position sensorless vector control of IM drive also becomes challenging when the ratio of inverter switching frequency to maximum modulation frequency is low. An improved procedure to design current controllers, and a closed-loop ux estimator are reviewed. These are utilized to design and implement successfully a position sensorless vector controlled IM drive, modulated with asynchronous third harmonic injected (THI) PWM at a constant switching frequency of 500 Hz. Sensorless vector control is also implemented successfully, when the inverter is modulated with synchronized THI PWM and the maximum switching frequency is limited to 500 Hz.

Voltage source inverter (VSI) fed induction motors are increasingly used in industrial and transportation applications as variable speed drives. However, VSIs generate non-sinusoidal voltages and hence result in harmonic distortion in motor current, motor heating, torque pulsations and increased acoustic noise. Most of these undesirable effects can be reduced by increasing the switching frequency of the inverter. This is not necessarily true for acoustic noise. Acoustic noise does not decrease monotonically with increase in switching frequency since the noise emitted depends on the proximity of harmonic frequencies to the motor resonant frequencies. Also there are practical limitations on the inverter switching frequency on account of device rating and losses. The switching frequency of many inverters often falls in the range 2 kHz - 6 kHz where the human ear is highly sensitive. Hence, the acoustic noise emission from the motor drive is of utmost important. Further, the acoustic noise emitted by the motor drive is known to depend on the waveform quality of the voltage applied. Hence, the acoustic performance varies with the pulse width modulation (PWM) technique used to modulate the inverter, even at the same modulation index. Therefore a comprehensive study on the acoustic noise aspects of induction motor drive is required. The acoustic noise study of the motor drive poses multifaceted challenges. A simple motor model is sufficient for calculation of total harmonic distortion (THD). A more detailed model is required for torque pulsation studies. But the motor acoustic noise is affected by many other factors such as stator winding distribution, space harmonics, geometry of stator and rotor slots, motor irregularities, structural issues controlling the resonant frequency and environmental factors. Hence an accurate model for acoustic noise would have to be very detailed and would span different domains such as electromagnetic fields, structural engineering, vibration and acoustics. Motor designers employ such detailed models along with details of the materials used and geometry to predict the acoustic noise that would be emitted by a motor and also to design a low-noise motor. However such detailed motor model for acoustic noise purposes and the necessary material and constructional details of the motor are usually not available to the user. Also, certain factors influencing the acoustic noise change due to wear and tear during the operational life of the motor. Hence this thesis takes up an experimental approach to study the acoustic noise performance of an inverter-fed induction motor at any stage of its operating life. A 10 kVA insulated gate bipolar transistor (IGBT) based inverter is built to feed the induction motor; a 6 kW and 2.3 kW induction motors are used as experimental motors. A low-cost acoustic noise measurement system is also developed as per relevant standards for measurement and spectral analysis of the acoustic noise emitted. For each PWM scheme, the current and acoustic noise measurements are carried out extensively at different carrier frequencies over a range of fundamental frequencies. The main cause of acoustic noise of electromagnetic origin is the stator core vibration, which is caused by the interaction of air-gap fluxes produced by fundamental current and harmonic currents. In this thesis, an experimental procedure is suggested for the acoustic noise characterization of an induction motor inclusive of determination of resonant frequencies. Further, based on current and acoustic noise measurements, a vibration model is proposed for the stator structure. This model is used to predict the acoustic noise pertaining to time harmonic currents with reasonable accuracy. Literature on motor acoustic noise mainly focuses on sinusoidal PWM (SPWM), conventional space vector PWM (CSVPWM) and random PWM (RPWM). In this thesis, acoustic noise pertaining to two bus-clamping PWM (BCPWM) schemes and an advanced bus-clamping PWM (ABCPWM) scheme is investigated. BCPWM schemes are mainly used to reduce the switching loss of the inverter by clamping any of the three phases to DC rail for 120◦ duration of the fundamental cycle. Experimental results show that these BCPWM schemes reduce the amplitude of the tonal component of noise at the carrier frequency, compared to CSVPWM. Experimental results with ABCPWM show that the overall acoustic noise produced by the motor drive is reduced at low and medium speeds if the switching frequency is above 3 kHz. Certain spread in the frequency spectrum of noise is also seen with both BCPWM and ABCPWM. To spread the acoustic noise spectrum further, many variable-frequency PWM schemes have been suggested by researchers. But these schemes, by and large, increase the current total harmonic distortion (THD) compared to CSVPWM. Thus, a novel variable-frequency PWM (VFPWM) method is proposed, which offers reduced current THD in addition to uniformly spread noise spectrum. Experimental results also show spread in the acoustic noise spectrum and reduction in the dominant noise components with the proposed VFPWM. Also, the current THD is reduced at high speeds of the motor drive with the proposed method.

Submitted by Renata Lopes (renatasil82@gmail.com) on 2016-07-12T12:29:15Z No. of bitstreams: 1 pedrosantosalmeida.pdf: 11306492 bytes, checksum: 80bd2f9ab4af41e3889b7bc91e4391b9 (MD5) / Approved for entry into archive by Adriana Oliveira (adriana.oliveira@ufjf.edu.br) on 2016-07-13T16:48:06Z (GMT) No. of bitstreams: 1 pedrosantosalmeida.pdf: 11306492 bytes, checksum: 80bd2f9ab4af41e3889b7bc91e4391b9 (MD5) / Made available in DSpace on 2016-07-13T16:48:06Z (GMT). No. of bitstreams: 1 pedrosantosalmeida.pdf: 11306492 bytes, checksum: 80bd2f9ab4af41e3889b7bc91e4391b9 (MD5) Previous issue date: 2012-03-23 / CAPES - Coordenação de Aperfeiçoamento de Pessoal de Nível Superior / Este trabalho apresenta um estudo acerca da alimentação de diodos emissores de luz (LEDs) a partir da rede elétrica empregando conversores eletrônicos com correção do fator de potência. O estudo visa o desenvolvimento de um conversor que pode ser aplicado em iluminação pública, que atenda às demandas típicas de alto fator de potência, alta eficiência, reduzido número de componentes, baixa distorção harmônica da corrente de entrada e possa atingir uma elevada vida útil, através da substituição de capacitores eletrolíticos no circuito de potência por capacitores de filme. É proposta uma nova topologia de conversor para implementar tal acionamento, baseado em uma integração entre dois estágios, que passam a compartilhar um único interruptor estático. Os conversores SEPIC e buck-boost operando em modo de condução descontínua (DCM) são escolhidos para compor cada um destes estágios, atuando o primeiro na correção do fator de potência e o segundo na regulação de corrente na carga. Uma metodologia de projeto que visa excluir os capacitores eletrolíticos é desenvolvida, partindo de dados fotométricos que permitem aplicar nos LEDs uma ondulação limite de 50% em amplitude, sem causar prejuízos ao seu desempenho fotométrico. Um protótipo de 70 W é apresentado, cujos resultados experimentais demonstram alto fator de potência (0,998), baixa distorção harmônica de corrente (3,2%) e alta eficiência (90,2%), enquanto empregando somente capacitores de filme metalizado, de longa vida útil, no circuito de potência. Uma abordagem das possibilidades de se implementar um controlador digital para o novo conversor proposto é feita, partindo de um modelo de pequenos sinais para o conversor operando em DCM. / This work presents a study regarding the feeding of light-emitting diodes (LEDs) from mains (grid power) employing electronic drivers with power factor correction. The study aims the development of an LED driver which can be applied to public and street lighting, complying with the typical demands of high power factor, high efficiency, reduced component count, low total harmonic distortion (THD) of input current and which can attain long lifespan, through the substitution of electrolytic capacitors within the power circuit by film capacitors. It is proposed a new converter topology to implement such driver, based on an integration between two stages which share a common static power switch. The SEPIC and buck-boost converters operating in discontinuous conduction mode (DCM) are chosen to make up each of these two stages, the first acting as a power factor corrector and the second as a load currentcontrolling stage. A design methodology which aims the exclusion of electrolytic capacitors is developed, stemming from photometric data which allow the LEDs to be operated with current ripples up to 50% in amplitude, without causing any harm to their photometric performance. A 70 W prototype is presented, whose experimental results demonstrate high power factor (0.998), low current harmonic distortion (3.2%) and high efficiency (90.2%), while employing only long-life metallised-film capacitors on the power circuit. An approach to the possibilities of implementing a digital controller for the proposed novel converter is done, starting from a small-signal model for the converter operating in DCM.

No description available.