AC main drives, such as cycloconverters, offer the possibility of higher speed and torque response over their DC counterparts. The price to be paid, however, is torque ripple which is a function of the operating frequency. Even a small value of ripple, at an underdamped plant resonant frequency, may be multiplied by the plant "Q" to a large enough value to cause trouble. Typical classical approaches used in the rolling mill industry to deal with mechanical resonance tend to fall apart with large values of time lag. We investigate a modified LQR/LQE approach using a torque sensor as the feedback element. The result is a low order SISO filter that suppresses the effects of the torque ripple on the underdamped plant. / Master of Science

Among the different multiphase ac drive solutions, one of the most widely reported in the literature is the six-phase machine. The machines can be realised into two different configurations, symmetrical and asymmetrical. For the symmetrical configuration, the stator winding consists of two sets of three-phase windings that are spatially shifted by 60 degrees where spatial displacement between any two consecutive phases is the same and equal to 60 degrees. For the asymmetrical configuration, the two sets of three-phase windings are spatially shifted by 30 degrees. As a result, the spatial shift between consecutive phases becomes non-equidistant. In this thesis, modulation techniques for both symmetrical and asymmetrical six-phase machines are investigated. The machines are configured in open-end winding configuration where both ends of the stator winding are connected to separate isolated inverters in a topology known as dual-inverter supply. Compared to conventional single-sided supply topology where one end of the winding is connected to an inverter while the other side is star-connected, some additional benefits are offered by the dual-inverter supply topology. First, fault tolerance of the drive is improved, since the supply is realised with two independent inverters. In case one of the inverters is faulted, the other can continue to provide power to the machine. Second, the same phase voltages can be achieved with half the dc-link voltages on the two inverter inputs compared to the single-sided supply, which can be useful in applications such as electric and hybrid electric vehicles and medium sized ships, where the dc voltage levels are limited. Further, due to the nature of the topology, additional diodes and capacitors like in the Neutral Point Clamped (NPC) and Flying Capacitor (FC) VSIs are not required. The latter results in a further advantage - capacitor voltage balancing techniques are not required. Two pulse width modulation (PWM) techniques for control of the dual-inverter supplied six-phase drives are proposed in this thesis. The first is a reference sharing algorithm where the inverters are modulated using reference voltage that is shared equally and unequally between the two modulators. For both symmetrical and asymmetrical six-phase drives, a better performance, in term of total harmonic distortion (THD) of phase voltage is obtained when the reference is shared unequally between the two modulators. The second technique is carrier-based modulation where the modulation of the two inverters is determined by the disposition of the carrier signals. Three variations of carrier signals disposition are investigated namely; the phase disposition (PD-PWM), alternate phase opposition disposition (APOD-PWM) and phase-shifted PWM (PS-PWM). For the symmetrical six-phase drive, the best phase voltage and current THDs are obtained using APOD-PWM while for asymmetrical six-phase drive, the APOD-PWM produces the worst current THD despite having the best voltage THD among the three methods. All the developed modulation techniques are analysed using simulations and experiments undertaken using a laboratory prototypes. The waveforms and spectra of phase voltage and load current obtained from the simulation and experimental works are presented in this thesis together with the THD of both the voltage and current over entire linear modulation range.

Diploma Thesis describes principle of AC motors. It shows method of the vector control, Clarke and Park transformation. The Thesis contains proposal control AC drives in higher speed than nominal.

A novel hybrid pulse-width modulation (PWM) update method is proposed to eliminate the effect of the one-step control time delay Td one without losing the full duty cycle range. Without the Td one to cause linear phase shifts that limit the control bandwidth and affect closed-loop stability, a very high quality digital current control can be achieved, such as a high closed current loop bandwidth, strong robustness against disturbances, ability to reach a very high fundamental frequency compared to switching frequency, etc. In a conventional digital control implementation, a sampling period (Tsamp) is allocated for the execution of samplings and computations, and the update of PWM outputs is delayed until the beginning of the following sampling period. This delayed PWM update method is the cause of the Td one. Instead of the delayed PWM update, if the PWM outputs are updated immediately after algorithm computations, then the effect of the Td one can be eliminated; however, the computation time delay Td comp from the current sampling instant through algorithm computations to the PWM update instant causes a reduced duty cycle range. Each of these two conventional PWM update methods has some shortcomings. A hybrid PWM update method is proposed to circumvent the aforementioned shortcomings and to incorporate only the advantages. The proposed method improves the performance by updating the PWM outputs multiple times during a Tsamp, whereas the PWM outputs are updated only one time during a Tsamp in the conventional methods. In spite of the simplicity of the proposed method, the performance improvements in stability, robustness and response characteristics are significant. On the other hand, the proposed method can be easily applied to many PWM based digital controls because of its simplicity. Additional to the hybrid PWM update method, a hybrid control method is proposed to optimize the sequence of control operations. It maximizes the current loops' robustness and minimizes the delay from the sampling of outer control loops' variables, such as voltage and speed, to the duty cycle update instant. The minimum delay enables the maximization of the outer control loops' bandwidth. Additionally, a corrective neutral offset voltage injection method is proposed to correct small PWM output deviations that may occur with the hybrid PWM update method. Utilizing a three-phase voltage source inverter with a permanent magnet synchronous machine as the platform, a deadbeat current control and a high speed ac drive experiments have been conducted to demonstrate the feasibility and validity. Notable results include a closed current loop response of one Tsamp with the deadbeat control and a 500 Hz current fundamental frequency with 1 kHz switching frequency in the high speed ac drive. / Ph. D.

La stabilité est un facteur très important dans tous les modes de fonctionnement pour un Système à Puissance Distribué (SPD). En SPD, les charges sont connectées au bus DC à travers d’un filtre entré LC. La plupart des charges de SPD d'avions présents une caractéristique de charge à puissance constante dans un domaine de fonctionnement dans laquelle ils sont étroitement contrôlés. Ainsi, elles peuvent être modélisées comme une résistance négative. Changement de la charge dans un sous-système peut conduire un système stable dans l'instabilité.Une solution pratique pour diminuer le risque d'instabilité est présentée dans cette thèse qui consiste à modifier le contrôle des convertisseurs ou système onduleur-moteur connecté au bus DC. Cette solution permet de stabiliser le système, même avec un condensateur plus petit. Dans la première partie de la thèse, une méthode linéaire est présentée qui permet étudier la stabilité locale d'un système onduleur-moteur connecté au réseau par un filtre LC et un redresseur. Une technique de compensation d’oscillation est utilisée pour améliorer la marge de stabilité du système et la taille de la capacité dc-link sans modifier la structure des boucles de courant ou de couple. Cette technique consiste à superposer une puissance stabilisant sur la puissance absorbée par le drive. Bien que les modèles linéaires puissent être employées avec succès pour décrire le comportement d'un système physique au niveau local, ils échouent souvent de fournir une caractérisation satisfaisante de large-signal. Dans la deuxième partie, deux méthodes pour la stabilisation large-signal du système électrique sont présentées. Dans la dernière partie, une nouvelle méthode, basée sur les spécifications dynamiques est proposée pour étudier la stabilité d'un système électrique en cascade / Stability is the first and very important factor in all modes of operation for a Distributed Power System (DPS). In DPS, loads are connected to the DC-bus through an input LC filter. Most of the loads in DPS of aircraft present a constant power load characteristic within a domain of operation in which they are tightly controlled. So they can be modeled as negative resistance. Change of the load in one subsystem may lead a stable system into instability. A practical solution to decrease the risk of instability presented in this thesis which consists in modifying the control of the converters or inverter-motor drive system connected to the DC-bus. This solution permits to stabilize the system even with a smaller size of capacitor. In the first part of the thesis, a linear method is presented which allows investigating local stability of an inverter-motor-drive system connected to the grid through an LC filter and a rectifier. An oscillation compensation technique is used to improve the stability margin of the system and the size of the dc-link capacitance without modifying structure of the torque or current loops. This technique consists in superposing a stabilizing power on the absorbed power by the drive. Although linear models can be successfully employed to locally describe the behavior of a physical system, they often fail to provide a satisfactory large signal characterization. In the second part, two methods for the large signal stabilization of the electrical system are presented. In the last part, a new method, based on dynamic specifications, is proposed to study the stability of a cascaded electric system

A voltage source inverter is commonly used to supply a variable frequency variable voltage to a three phase induction motor in a variable speed application. A suitable pulse width modulation (PWM) technique is employed to obtain the required output voltage in the line side of the inverter. Real-time methods for PWM generation can be broadly classified into triangle comparison based PWM (TCPWM) and space vector based PWM (SVPWM). In TCPWM methods such as sine-triangle PWM, three phase reference modulating signals are compared against a common triangular carrier to generate the PWM signals for the three phases. In SVPWM methods, a revolving reference voltage vector is provided as voltage reference instead of three phase modulating waves. The magnitude and frequency of the fundamental component in the line side are controlled by the magnitude and frequency, respectively, of the reference vector. The fundamental line side voltage is proportional to the reference magnitude during linear modulation. With sine-triangle PWM, the highest possible peak phase fundamental voltage is 0.5Vdc, where Vdc is the DC bus voltage, in the linear modulation zone. With techniques such as third harmonic injection PWM and space vector based PWM, the peak phase fundamental voltage can be as high as (formula) (i.e., 0:577Vdc)during linear modulation. To increase the line side voltage further, the operation of the VSI must be extended into the overmodulation region. The overmodulation region extends upto the six-step mode, which gives the highest possible ac voltage for a given (formula). In TCPWM based methods, increasing the reference magnitude beyond a certain level leads to pulse dropping, and gradually leads to six-step operation. However, in SVPWM methods, an overmodulation algorithm is required for controlling the line-side voltage during overmodulation and to achieve a smooth transition from PWM to six-step mode. Numerous overmodulation algorithms have been proposed in the literature for space vector modulated inverter. A well known algorithm among these divides the overmodulation zone into two zones, namely zone-I and zone-II. This is termed as the 'existing overmodulation algorithm' here. This algorithm is modified in the present work to reduce computational burden without much increase in the line current distortion. During overmodulation, the fundamental line side voltage and the reference magnitude are not proportional, which is undesirable from the control point of view. The present work ensures a linear relationship between the two. Apart from the fundamental component, the inverter output voltage mainly consists of harmonic components at high frequencies (around switching frequency and the integral multiples) during linear modulation. However, during overmodulation, low order harmonic components such as 5th, 7th, 11th, 13th etc., are also present in the output voltage. These low order harmonic voltages lead to low order harmonic currents in the motor. The sum of the lower order harmonic currents is termed as 'lower order current ripple'. The present thesis proposes a method for estimation of lower order current ripple in real-time. In closed loop current control, the motor current is fed back to the current controller. During overmodulation, the motor current contains low order harmonics, which appear in the current error fed to the controller. These harmonic currents are amplified by the current error amplifier deteriorating the performance of the drive. It is possible to filter the lower order harmonic currents before being fed back. However, filtering introduces delay in the current loop, and reduces the bandwidth even during linear modulation. In the present work, the estimated lower order current ripple is subtracted from the measured current before the latter is fed back to the controller. The estimation of lower order current ripple and the proposed current control are verified through simulation using MATLAB/SIMULINK and also experimentally on a laboratory prototype. The experimental setup comprises of a field programmable gate arrays (FPGA) based digital controller, an IGBT based inverter and a four-pole squirrel cage induction motor. (Pl refer the original document for formula)

This thesis deals with state estimation methods for AC drives sensorless control and with possibilities of the estimation. Conditions for observability for a synchronous drive were derived, as well as conditions for the moment of inertia and the load torque observability for both drive types - synchronous and asynchronous. The possibilities of the estimation were confirmed by experimental results. The covariance matrices for all filters were found using an EM algorithm. Both drives were also identified. The algoritms used for state estimation are Extended Kalman Filter, Unscented Kalman Filter, Particle Filters and Moving Horizon Estimator.

In high power induction motor drives, the switching frequency of the inverter is quite low due to the high losses in the power devices. Real-time PWM strategies, which result in reduced harmonic distortion under low switching frequencies and have maximum possible DC bus utilisation, are developed for such drives in the present work. The space vector approach is taken up for the generation of synchronised PWM waveforms with 3-Phase Symmetry, Half Wave Symmetry and Quarter Wave Symmetry, required for high-power drives. Rules for synchronisation and the waveform symmetries are brought out. These rules are applied to the conventional and modified forms of space vector modulation, leading to the synchronised conventional space vector strategy and the Basic Bus Clamping Strategy-I, respectively. Further, four new synchronised, bus-clamping PWM strategies, namely Asymmetric Zero-Changing Strategy, Boundary Sampling Strategy-I, Basic Bus Clamping Strategy-II and Boundary Sampling Strategy-II, are proposed. These strategies exploit the flexibilities offered by the space vector approach like double-switching of a phase within a subcycle, clamping of two phases within a subcycle etc. It is shown that the PWM waveforms generated by these strategies cannot be generated by comparing suitable 3-phase modulating waves with a triangular carrier wave. A modified two-zone approach to overmodulation is proposed. This is applied to the six synchronised PWM strategies, dealt with in the present work, to extend the operation of these strategies upto the six-step mode. Linearity is ensured between the magnitude of the reference and the fundamental voltage generated in the whole range of modulation upto the six-step mode. This is verified experimentally. A suitable combination of these strategies leads to a significant reduction in the harmonic distortion of the drive at medium and high speed ranges over the conventional space vector strategy. This reduction in harmonic distortion is demonstrated, theoretically as well as experimentally, on a constant V/F drive of base frequency 50Hz for three values of maximum switching frequency of the inverter, namely 450Hz, 350Hz and 250Hz. Based on the notion of stator flux ripple, analytical closed-form expressions are derived for the harmonic distortion due to the different PWM strategies. The values of harmonic distortion, computed based on these analytical expressions, compare well with those calculated based on Fourier analysis and those measured experimentally.

MULTILEVEL inverters are the preferred choice of converters for electronic power conversion for high power applications. They are gaining popularity in variety of industrial applications including electric motor drives, transportation, energy management, transmission and distribution of power. A large portion of energy conversion systems comprises of multilevel inverter fed induction motor drives. The multilevel inverters are ideal for such applications, since the switching frequency of the devices can be kept low. In conventional two level inverters, to get nearly sinusoidal phase current waveform, the switching frequency of the inverter is increased and the harmonics in the currents are pushed higher in the frequency spectrum to reduce the size and cost of the filters. But higher switching frequency has its own drawbacks – in particular for medium voltage, high power applications. They cause large dv_/ dt stresses on the motor terminals and the switching devices, leading to increased electromagnetic interference (EMI) problems and higher switching losses. Harmonics in the motor currents can further be minimized by adopting dodecagonal voltage space vector (SV) switching (12-sided polygon). In case of dodecagonal SV switching, the fifth and seventh order (6n , 1, n = odd) harmonics are completely eliminated for the full modulation range including over modulation and twelve step operation in the motor phase voltages and currents. In addition to low order harmonic current suppression, the linear modulation range for dodecagonal SV switching is also more by 6% when compared to that of the conventional hexagonal SV switching. The dodecagonal voltage SV structure is made possible by connecting two inverters with DC-link voltages Vd and 0:366Vd on either side of an open-end winding induction motor. The dodecagonal space vector switching can be used to produce better quality phase voltage and current waveforms and overcome the problem of low order fifth and seventh harmonic currents and to improve the range for linear modulation while reducing the switching frequency of the inverters when compared to that of the conventional hexagonal space vector based inverters. This thesis focuses on three aspects of multilevel dodecagonal space vector structures (i) Two new power circuit topologies that generate a multilevel dodecagonal voltage space vector structure with symmetric triangles, (ii) A multilevel dodecagonal SV structure with nineteen concentric dodecagons, (iii) Pulse width modulation (PWM) timing calculation methods for a general N-level dodecagonal SV structure. (i) Two new power circuit topologies capable of generating multilevel dodecagonal voltage space vector structure with symmetric triangles with minimum number of DC link power supplies and floating capacitor H-bridges are proposed. The first power topology is composed of two hybrid cascaded five level inverters connected to either side of an open end winding induction machine. Each inverter consists of a three level neutral point clamped (NPC) inverter, cascaded with an isolated capacitor fed H-bridge making it a five level inverter. The second topology is a hybrid topology for a normal induction motor (star or delta connected), where the power is fed to the motor only from one side. The proposed scheme retains all the advantages of multilevel topologies as well the advantages of the dodecagonal voltage space vector structure. Both topologies have inherent capacitor balancing for floating H-bridges for all modulation indices including transient operations. The proposed topologies do not require any pre-charging circuitry for startup. PWM timing calculation method for space vector modulation is also explored in this chapter. Due to the symmetric arrangement of congruent triangles within the voltage space vector structure, the timing computation requires only the sampled reference values and does not require any iterative searching, off-line computation, look-up tables or angle estimation. Experimental results for steady state operation and transient operation are also presented to validate the proposed concept. (ii) A multilevel dodecagonal voltage space vector structure with nineteen concentric do-decagons is proposed for the first time. This space vector structure is achieved by connecting two sets of asymmetric hybrid five level inverters on either side of an open-end winding induction motor. The dodecagonal structure is made possible by proper selection of DC-link voltages and switching states of the inverters. In addition to that, a generic and simple method for calculation of PWM timings using only sampled reference values (v and v ) is proposed. This enables the scheme to be used for any closed loop application like vector control. Also, a new switching technique is proposed which ensures minimum switching while eliminating the fifth and seventh order harmonics and suppressing the eleventh and thirteenth harmonics, eliminating the need for bulky filters. The motor phase voltage is a 24-stepped waveform for the entire modulation range thereby reducing the number of switchings of the individual inverter modules. Experimental results for steady state operation, transient operation including start-up have been presented and the results of Fast Fourier Transform (FFT) analysis is also presented for validating the proposed concept. (iii) A method to obtain PWM timings for a general N-level dodecagonal voltage space vector structure using only sampled reference values is proposed. Typical methods that are used to find PWM timings for dodecagonal SV structures use modulation index and the reference vector angle, to get the timings T1 and T2 using trigonometric calculations. This method requires look-up tables and is difficult to implement in closed loop systems. The proposed method requires only two additions to compute these timings. For multilevel case, typical iterative methods need timing calculations (matrix multiplications) to be performed for each triangle. The proposed method is generic and can be extended to any number of levels with symmetric structures and does not require any iterative searching for locating the triangle in which the tip of the reference vector lies. The algorithm outputs the triangle number and the PWM timing values of T0, T1 and T2 which can be set as the compare values for any carrier based PWM module to obtain space vector PWM like switching sequences. Simulation and experimental results for steady state and transient conditions have been presented to validate the proposed method. A 3.7 kW, 415 V, 50 Hz, 4-pole open-end winding induction motor was used for the experimental studies. The semiconductor switches that were used to realize the power circuit for the experiment were 75 A, 1200 V insulated-gate bipolar transistor (IGBT) half-bridge modules (SKM75GB12T4). Opto-isolated gate drivers with desaturation protection (M57962L) were used to drive the IGBTs. For the speed control and PWM timing computation a digital signal processor (DSP-TMS320F28335) with a clock frequency of 150 MHz was used. For modulation frequencies 10 Hz and below, a constant sampling frequency of 1 kHz was used as the frequency modulation ratio is high. For modulation frequencies above 10 Hz, synchronous PWM strategy was used. The time duration Ts is the sampling interval for which the timings T1 , T2 and T0 are calculated. As in the case of any synchronous PWM method, the duration of sampling time (Ts) is a function of the fundamental frequency of the modulating signal. In this case, Ts = 1_.fm • 12n) sec. where fm is fundamental frequency in Hertz and ‘n’ is the number of samples per 30ý dodecagonal sector. The PWM timings and the triangle data (from the DSP) is fed to field programmable gate array (FPGA) (SPARTAN XC3S200) clocked at 50 MHz where the actual gating pulses are generated. The capacitor balancing algorithm and the dead-time modules were implemented within FPGA. No external hardware was used for generation of dead-time. The dead-time block generates a constant dead-time of 2 s for all the switches. Extensive testing was done for steady state operations and transient operations including quick acceleration and start-up to validate the proposed concepts. With the advantages like extension of linear modulation range, elimination of fifth and seventh harmonics in phase voltages and currents for the full modulation range, suppression of eleventh and thirteenth harmonics in phase voltages and currents, reduced device voltage ratings, lesser dv_dt stresses on devices and motor phase windings, lower switching frequency, inherent cascaded H-bridge (CHB) capacitor balancing, the proposed space vector structures, the inverter power circuit topologies, the switching techniques and the PWM timing calculation methods can be considered as viable schemes for medium voltage, high power motor drive applications.