Tese de mestrado. Redes e Serviços de Comunicação. Faculdade de Engenharia. Universidade do Porto. 2005

Tese de mestrado integrado. Engenharia Electrotécnica e de Computadores (Major Telecomunicações). Faculdade de Engenharia. Universidade do Porto. 2009

<p>The final thesis named Tracking in Sensor Networks was created by the company Instrument control Sweden. The thesis work is to create a plug-in to an already developed software pro- gram, SkyView. Via the software program one should be able to control an IP-camera from AXIS, model 215 PTZ, with the appropriate protocol over a network.  An Application Programming Interface, API, was used to easily control the camera through SkyView. The interface is called VAPIX and is used to all cameras from AXIS. VAPIX sup- ports Hyper Text Transfer Protocol, HTTP, and Real Time Streaming Protocol, RTSP.  The video was sent through the camera with RTSP, thus an investigation resulted in that the protocol was best suited at streaming video. Steering commands to the camera was sent via HTTP. A small program was written, which was then integrated to SkyView. Features to be able to control the camera with the keyboard, mouse and a joystick were implemented. Zoom, bright- ness, focus and some more features were also added. The problem with the delay should be dealt with as soon as possible.</p>

An enhancement of probability packet marking (PPM) used to trace back the DoS attacker is proposed by this paper. Our work is based on the probabilistic packet marking algorithm by Savage[1] in which an attack graph can be reconstructed by a victim site. Furthermore, we discuss some routers which do not support PPM in attacked path called non-PPM router. We use algorithm to recover one and two successive non-PPM routers. Recover three and four successive non-PPM routers by using IP RR (record routing) option. Five successive non-PPM routers and above are between two PPM routers, we discuss about Loosen Source Routing that record all traveled IP addresses into IP header. The temp table record edges which produced by proposed algorithm. And the hop table records which path the packet come from. Before the PPM system run, routers send probe packets we proposed above to recover the incomplete attack path.

SOC (System-On-Chip) designs are more and more popular, concurrently, more and more new challenges system integrators will meet. One out of these challenges is testing problem. Our research is focus on how to testing and debugging the microprocessor cores that embedded in an SOC. Not only test the microprocessor cores but also test the interconnecting wire among these embedded microprocessor cores. This thesis explores architectural alternatives in the integration of embedded in-circuit emulation (ICE) into an SOC chip with multiple micro-controller/processor cores. The alternatives include distributed, centralized and hierarchical styles. Advantages and disadvantages of these alternatives are analyzed.

This thesis was about investigating if it is feasible to implement an IP-forwarding data plane on a GPU. A GPU is energy efficient compared to other more powerful processors on the market today and should in theory be efficient to use for routing purposes. An IP-forwarding data plane consist of several things where we focused on some of the concepts. We have implemented IP-forwarding lookup operations, packet header changes, prioritization between different packets and a traffic shaper to restrict the packet throughput. To test these concepts we implemented a prototype, on a Tegra platform, in CUDA and evaluated its performance. We are able to forward 28 Mpackets/second with a best case latency of 27 µS given local simulated packets. The conclusions we can draw of this thesis work is that using a GPU for IP-forwarding purposes seems like an energy efficient solution compared to other routers on the market today. In the thesis we also tried the concept of only launching the GPU kernel once and let it be infinite which shows promising results for future work.

From the initial implementations for the DEC PDP-11 to those of today done for commodity PICs, the TCP/IP code stack continues to work its way into a smaller and more omnipresent class of devices. One shortcoming of current devices on the leading edge of this trend is that they belong more to the microcontroller categories, which typically lack any appreciable signal processing capability. Applications such as consumer electronics and wireless sensor networks could benefit greatly from single-chip network-capable devices which are based on a Digital Signal Processing (DSP) core rather than a microcontroller. This report details the design and implementation of a partial TCP/IP code stack intended for such a DSP. / text

ITC/USA 2014 Conference Proceedings / The Fiftieth Annual International Telemetering Conference and Technical Exhibition / October 20-23, 2014 / Town and Country Resort & Convention Center, San Diego, CA / As telemetry transport systems move inexorably closer to a unified telemetry-over-IP approach, the operators and engineers who have traditionally deferred to a separate communications group can benefit from a more comprehensive understanding of the intricacies of the transport medium and protocol. Ethernet, and more specifically IP network hardware, has gained increased robustness, as well as much of the reliability enhancing functionality of more venerable transport solutions, but with these increasingly integrated feature sets comes an emphasized demand on the telemetry systems operator to be able to configure the telemetry transport network devices in more dynamic environments. This paper will seek to serve as a handbook for the telemetry community, guiding discussions of the strengths, weaknesses, legacy, and future outlook of this transport methodology both within and without the groups involved in most range telemetry transport environments.

Stuttgart, Univ., Diplomarb., 1999.

Zugl.: Stuttgart, Universiẗat, Diss., 2004.