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Banyan networks comprise a large class of networks that have been used for interconnection in large-scale multiprocessors and telephone switching systems. Regular variants of Banyan networks, such as delta and butterfly networks, have been used in multiprocessors such as the IBM RP3 and the BBN Butterfly. Analysis of the performance of Banyan networks has typically focused on these regular variants. We present a methodology for performance analysis of unbuffered Banyan multistage interconnection networks. The methodology has two novel features: it allows analysis of networks where some inputs are more likely to be active than others, and allows analysis of Banyan networks of arbitrary topology.

This thesis is concerned with architecture for long term general purpose computers. The work is based on current trends in machine architecture and technology. Projections from these generated "Architectural Soups". An Architectural Soup has the potential to emulate many different machine architectures. The characteristics of this class of machine are, three dimensional, simple cells and a simple communications topology, which can be reconfigured at a very low level. This thesis aims to show potential usefulness and viability of machines with such capability. Methods of programming are considered, and important design issues are investigated. A specific implementation architecture is described and illustrated through simulation. An assessment is made of the architecture and of the simulator used. In addition, the implementation architecture is used as the basis for a VLSI design, which shows the simplicity of a Soup cell, and provides estimates of the possible number of cells in future machines.

Like many other multimedia applications, image compression involves a significant amount of data processing for coding images. Sophisticated general-purpose processors with parallel architectures and advanced cache systems can be dedicated to enhancing performance for serial multimedia applications through parallelization. This thesis describes parallelization of the JasPer reference software for the JPEG-2000 image compression standard and presents results from simulation, and from hardware execution on a multicore processor where speedups of more than 2 are obtained with 4 processors. Results from execution and cache behavior analysis are presented to establish the expected speedup and to further characterize JasPer execution. The JasPer encoding process has been analyzed on a single processor for both simulated and hardware execution in order to obtain more insights into application behavior. On recent hardware platforms, the significant contributors to the total execution time have been identified through profiling. The granularity of parallelism for parallelizable loops have been analyzed for execution on real hardware. Cache behavior and memory access pattern have been studied closely for the simulated execution. To facilitate parallelization, selected parallelizable loops have been transformed in order to assist the partitioning of loop iterations for parallel execution and to increase workload granularity and reduce synchronization overhead. These modifications include loop index and body transformation, and loop fusion. A memory access pattern tracking feature has also been introduced for serial and parallel execution of a program in simulation. This feature tracks the number of memory accesses in a particular data region during a particular interval of time in order to gain additional insights into execution behavior. The multithreaded execution of the parallelized JasPer encoder presents a relatively balanced workload which indicates a reasonable efficiency for parallel execution. The generated images have been compared against their original images by using analytical tools to ensure the image quality and to verify correctness. / Thesis (Master, Electrical & Computer Engineering) -- Queen's University, 2011-10-29 00:10:43.437

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At the heart of many power system computations lies the solution of a large sparse set of linear equations. These equations arise from the modelling of the network and are the cause of a computational bottleneck in power system analysis applications. Efficient sequential techniques have been developed to solve these equations but the solution is still too slow for applications such as real-time dynamic simulation and on-line security analysis. Parallel computing techniques have been explored in the attempt to find faster solutions but the methods developed to date have not efficiently exploited the full power of parallel processing. This thesis considers the solution of the linear network equations encountered in power system computations. Based on the insight provided by the elimination tree, it is proposed that a novel matrix structure is adopted to allow the exploitation of parallelism which exists within the cutset of a typical parallel solution. Using this matrix structure it is possible to reduce the size of the sequential part of the problem and to increase the speed and efficiency of typical LU-based parallel solution. A method for transforming the admittance matrix into the required form is presented along with network partitioning and load balancing techniques. Sequential solution techniques are considered and existing parallel methods are surveyed to determine their strengths and weaknesses. Combining the benefits of existing solutions with the new matrix structure allows an improved LU-based parallel solution to be derived. A simulation of the improved LU solution is used to show the improvements in performance over a standard LU-based solution that result from the adoption of the new techniques. The results of a multiprocessor implementation of the method are presented and the new method is shown to have a better performance than existing methods for distributed memory multiprocessors.

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