Chip-scale photonics has emerged as an exciting field which can potentially solve many of the problems plaguing the high-performance computing industry, from large-scale to embedded. In theory, photonics is a superior communication medium because of its higher bandwidth density using wave-division multiplexing and bandwidth-power translucency to distance traveled. In practice, physical-layer design and engineering issues such as optical loss, crosstalk, and packaging have slowed its entry into widespread adoption at the chip and board scale. In this work, we present these issues and potential design improvements. The major contributions, however, are the tools and methods we have developed for the design of photonic interconnection networks, including a system-level simulator and CAD and modeling environment for layout, both of which are publicly available to the research community.

This dissertation introduces a new communication paradigm, neighborcast, for vehicular ad hoc networks and proposes a new communication protocol, reliable neighborcast protocol (RNP), to implement the paradigm. Vehicular applications such as collision avoidance can benefit from allowing vehicles to communicate with their nearby vehicles in order to coordinate movements. Neighborcast is a new paradigm for communications between each vehicle and all nearby vehicles that are within a specified distance from it i.e., its neighbors. In neighborcast, each vehicle has its own set of vehicles with which it wants to communicate i.e., the set of its neighbors, which is different from that of other vehicles. Our proposed communication protocol, RNP, is aimed at providing reliable neighborcast communications. It provides guaranteed message delivery from each vehicle in a vehicular ad hoc network to all of its neighbors within a bounded delay, ensures that all the neighbors that receive the same messages sequence them in the same order and use each of them at the same time, and provides the neighbors the knowledge of whether all of the other neighbors have received the message or which neighbors are missing the message. The implementation of RNP is significantly different from reliable multicast/broadcast protocols. In a reliable multicast/broadcast protocol, all communicating vehicles are in one group. But in our RNP, the group size is constrained to limit the communication delay, so we cannot have all vehicles in one group. As a result, we organize vehicles into several overlapping groups and each vehicle may communicate in more than one overlapping group. RNP is created as an overlay protocol on top of overlapping broadcast groups that use a modified version of a recently invented reliable broadcast protocol, M-RBP, and transfers the guarantees provided by the modified M-RBP from the broadcast group level to the neighborhood level. RNP is composed of two parts. The first is the self-organizing protocol that organizes vehicles into overlapping broadcast groups that use the modified version of M-RBP. The self-organizing protocol ensures that each vehicle is always a member of at least one broadcast group containing itself and all of its neighbors. This way, it can reach all of its neighbors by transmitting messages in one broadcast group, resulting in the same message sequencing for all neighbors. The self-organizing protocol also limits the size of each broadcast group to limit the message delivery delay, limits the number of broadcast groups of which a vehicle is a member to limit the number of recovery messages, and moves the broadcast groups with the vehicles to limit the rate at which a vehicle changes groups. The second part of RNP is the mechanism that transfers the guarantees from M-RBP to provide the RNP guarantees. In this dissertation, we also show an example of using RNP in conjunction with sensors to avoid rear-end collisions. We propose a simple set of rules for using RNP with sensors to automatically maintain a safe following distance, provide warnings of emergency situations, and negotiate the safe deceleration rates among nearby communicating vehicles. We quantify the highway capacity improvement from using RNP and compare it with that of using sensors alone.

This work investigates signal encoding in, and architectures of, digital signal processing systems that function in continuous time (CT). Unlike conventional digital signal processors (DSPs), which rely on a clock to dictate the sampling times of an analog-to-digital converter (ADC) and to provide the tap delay timing, CT DSPs function entirely in continuous time, without a sampling or a synchronizing clock. The samples of a CT DSP system are generated and processed only when some measure of the input signal crosses a predetermined threshold. The effective sampling rate and the dynamic power dissipation of a CT digital system automatically adapt to the activity of the input signal. The properties of signals sampled in continuous time are investigated in this thesis. A technique for reducing the effective sampling rate of a CT system is presented, in which the digital signal encoding is varied by adjusting the resolution according to a property of the input. A variable-resolution system leads to a decrease in the number of samples generated, a reduction in the power dissipation and a reduction in the effective chip area of a CT DSP, all without sacrificing in-band performance. The properties of several asynchronous signal-driven sampling techniques are analyzed and compared. The architecture and signal encoding of CT DSPs for signals in the lower gigahertz frequency range are investigated, with consideration of speed and accuracy limitations in the context of submicron CMOS technologies. A per-edge digital signal encoding technique is developed, which bypasses timing problems of processing high-speed digital signals; the properties of per-edge encoded signals are discussed. The design considerations of a low-resolution per-edge-encoded gigahertz-range CT DSP are discussed and an implementation for a possible application is detailed. A prototype chip has been fabricated in ST 65 nm CMOS technology, which has a compact processor core area of 0.073 mm^2. The implemented CT digital processor achieves SNDR of over 20 dB with 3 bits of resolution and a maximum usable -3 dB bandwidth of 0.8 GHz to 3.2 GHz. The processor can be configured as a one-tap to six-tap CT FIR filter and has an active power dissipation that varies from 0.27 mW to 9.5 mW, depending on the amplitude and frequency of the input signal.

We present group and phase velocity control for the photonic integrated circuits with an emphasis on two-dimensional photonic crystal devices in this thesis. We describe the theory, analytical and numerical designs, and experimental characterization of silicon nanophotonic devices both in classical and quantum space. These devices which include negatively refractive photonic crystals, coherently interacting nano-resonators, power splitters, and interferometers provide phase-delay and time-delay tunability that lead to new functionalities in photonic integrated circuits for on-chip information processing, optical computation and communications. The high performance designs are all compatible with CMOS fabrication processes and can be easily integrated for infrared telecommunication applications. Here, we study photonic crystals in terms of the wavelengths at which they are transparent as well as they have a band-gap. This is particularly important in this work as most of the research on photonic crystals to date has focused more on the band gaps, ignoring effects that occur in transparent wavelengths. We show that a number of applications such as zero-phase delay lines and adjustable filters can be realized based on their polarization-dependent properties and nontrivial phase effects in the transparent region and dynamic storage of light can be achieved via optical analogue of electromagnetically induced transparency in an originally non-transmitting wavelength region.

Organic thin film transistors and ferroelectric polymer (polyvinylidene difluoride) sheet material are integrated to form various sensors for stress/strain, acoustic wave, and Infrared (heat) sensing applications. Different from silicon-based transistors, organic thin film transistors can be fabricated and processed in room-temperature and integrated with a variety of substrates. On the other hand, polyvinylidene difluoride (PVDF) exhibits ferroelectric properties that are highly useful for sensor applications. The wide frequency bandwidth (0.001 Hz to 10 GHz), vast dynamic range (100n to 10M psi), and high elastic compliance (up to 3 percent) make PVDF a more suitable candidate over ceramic piezoelectric materials for thin and flexible sensor applications. However, the low Curie temperature may have impeded its integration with silicon technology. Organic thin film transistors, however, do not have the limitation of processing temperature, hence can serve as transimpedance amplifiers to convert the charge signal generated by PVDF into current signal that are more measurable and less affected by any downstream parasitics. Piezoelectric sensors are useful for a range of applications, but passive arrays suffer from crosstalk and signal attenuation which have complicated the development of array-based PVDF sensors. We have used organic field effect transistors, which are compatible with the low Curie temperature of a flexible piezoelectric polymer,PVDF, to monolithically fabricate transimpedance amplifiers directly on the sensor surface and convert the piezoelectric charge signal into a current signal which can be detected even in the presence of parasitic capacitances. The device couples the voltage generated by the PVDF film under strain into the gate of the organic thin film transistors (OFET) using an arrangement that allows the full piezoelectric voltage to couple to the channel, while also increasing the charge retention time. A bipolar detector is created by using a UV-Ozone treatment to shift the threshold voltage and increase the current of the transistor under both compressive and tensile strain. An array of strain sensors which maps the strain field on a PVDF film surface is demonstrated in this work. The strain sensor experience inspires a tone analyzer built using distributed resonator architecture on a tensioned piezoelectric PVDF sheet. This sheet is used as both the resonator and detection element. Two architectures are demonstrated; one uses distributed directly addressed elements as a proof of concept, and the other integrates organic thin film transistor-based transimpedance amplifiers monolithically with the PVDF sheet to convert the piezoelectric charge signal into a current signal for future applications such as sound field imaging. The PVDF sheet material is instrumented along its length and the amplitude response at 15 sites is recorded and analyzed as a function of the frequency of excitation. The determination of the dominant frequency component of an incoming sound is demonstrated using linear system decomposition of the time-averaged response of the sheet using no time domain detection. Our design allows for the determination of the spectral composition of a sound using the mechanical signal processing provided by the amplitude response and eliminates the need for time-domain electronic signal processing of the incoming signal. The concepts of the PVDF strain sensor and the tone analyzer trigger the idea of an active matrix microphone through the integration of organic thin film transistors with a freestanding piezoelectric polymer sheet. Localized acoustic pressure detection is enabled by switch transistors and local transimpedance amplification built into the active matrix architecture. The frequency of detection ranges from DC to 15KHz; the bandwidth is extended using an architecture that provides for virtually zero gate/source and gate/drain capacitance at the sensing transistors and low overlap capacitance at the switch transistors. A series of measurements are taken to demonstrate localized acoustic wave detection, high pitch sound diffraction pattern mapping, and directional listening. This system permits the direct visualization of a two dimensional sound field in a format that was previously inaccessible. In addition to the piezoelectric property, pyroelectricity is also exhibited by PVDF and is essential in the world of sensors. An integration of PVDF and OFET for the IR heat sensing is demonstrated to prove the concept of converting pyroelectric charge signal to a electric current signal. The basic pyroelectricity of PVDF sheet is first examined before making a organic transistor integrated IR sensor. Then, two types of architectures are designed and tested. The first one uses the structure similar to the PVDF strain sensor, and the second one uses a PVDF capacitor to gate the integrated OFETs. The conversion from pyroelectric signal to transistor current signal is observed and characterized. This design provides a flexible and gain-tunable version for IR heat sensors.

Photonic technology is becoming an increasingly attractive solution to the problems facing today's electronic chip-scale interconnection networks. Recent progress in silicon photonics research has enabled the demonstration of all the necessary optical building blocks for creating extremely high-bandwidth density and energy-efficient links for on- and off-chip communications. From the feasibility and architecture perspective however, photonics represents a dramatic paradigm shift from traditional electronic network designs due to fundamental differences in how electronics and photonics function and behave. As a result of these differences, new modeling and analysis methods must be employed in order to properly realize a functional photonic chip-scale interconnect design. In this work, we present a methodology for characterizing and modeling fundamental photonic building blocks which can subsequently be combined to form full photonic network architectures. We also describe a set of tools which can be utilized to assess the physical-layer and system-level performance properties of a photonic network. The models and tools are integrated in a novel open-source design and simulation environment called PhoenixSim. Next, we leverage PhoenixSim for the study of chip-scale photonic networks. We examine several photonic networks through the synergistic study of both physical-layer metrics and system-level metrics. This holistic analysis method enables us to provide deeper insight into architecture scalability since it considers insertion loss, crosstalk, and power dissipation. In addition to these novel physical-layer metrics, traditional system-level metrics of bandwidth and latency are also obtained. Lastly, we propose a novel routing architecture known as wavelength-selective spatial routing. This routing architecture is analogous to electronic virtual channels since it enables the transmission of multiple logical optical channels through a single physical plane (i.e. the waveguides). The available wavelength channels are partitioned into separate groups, and each group is routed independently in the network. Each partition is spectrally multiplexed, as opposed to temporally multiplexed in the electronic case. The wavelength-selective spatial routing technique benefits network designers by provider lower contention and increased path diversity.

While extremely scaled CMOS transistors are believed to cause many design concerns especially for conventional analog circuits, CMOS technology scaling, on the other hand, has also opened up new opportunities for analog and mixed-mode circuit designs to mitigate design challenges by the speed improvement and the high density of the nanometer devices. Phase-locked-loop-based frequency synthesizers are essential building blocks in almost all the communication systems. The design of PLLs is a true mixed signal design challenge covering from high speed analog and RF blocks (VCO), to high speed digital blocks (dividers), to low speed analog (charge pump and loop filter) and low speed digital (phase frequency detector) circuits. In this thesis, we study design challenges and present corresponding solutions to realize PLLs in the nano-scale CMOS era. In particular we focus on supply voltage scaling, area scaling, ultra-wide frequency range, and ultra-low noise performance. An ultra low voltage (ULV) 2.5-GHz GFSK modulator implemented in a 90-nm CMOS technology using only standard digital regular Vt (RVT) devices will first be introduced to address robustness concerns and speed issues due to the supply voltage scaling (down to 0.5V). Then, a 2.5-GHz ultra-compact (150um x 280um) analog PLL implemented in a 45-nm CMOS technology with a fully integrated LC-VCO and an on-chip passive R-C loop filter will further be used to show that area scaling can indeed be achieved for a PLL through a rigorous area-scaling scheme of LC oscillators and a new loop filter structure. New emerging applications such as software-defined radios or highly integrated test instrumentation require the PLL synthesizer to have ultra wide bandwidth and ultra low phase noise. We will present the approaches to mitigate these challenging design objectives by exploiting the capabilities of nanometer transistors. A wideband synthesizer covering from 125MHz to 32GHz with a constant performance across the entire frequency range will be presented; the scaling schemes and design methodologies to achieve constant noise performance across the ultra-wide frequency range will be discussed. Finally, an ultra low noise fractional-N synthesizer will be presented to show how low phase noise fractional-N frequency synthesis can be achieved by taking the full advantage of nano-scale CMOS transistors.

Growing demands on future data centers and high-performance computing systems are driving the development of processor-memory interconnects with greater performance and flexibility than can be provided by existing electronic interconnects. A redesign of the systems' memory devices and architectures will be essential to enabling high-bandwidth, low-latency, resilient, energy-efficient memory systems that can meet the challenges of exascale systems and beyond. By leveraging an optics-based approach, this thesis presents the design and implementation of an optically-connected memory system that exploits both the bandwidth density and distance-independent energy dissipation of photonic transceivers, in combination with the flexibility and scalability offered by optical networks. By replacing the electronic memory bus with an optical interconnection network, novel memory architectures can be created that are otherwise infeasible. With remote optically-connected memory nodes accessible to processors as if they are local, programming models can be designed to utilize and efficiently share greater amounts of data. Processors that would otherwise be idle, being starved for data while waiting for scarce memory resources, can instead operate at high utilizations, leading to drastic improvements in the overall system performance. This work presents a prototype optically-connected memory module and a custom processor-based optical-network-aware memory controller that communicate transparently and all-optically across an optical interconnection network. The memory modules and controller are optimized to facilitate memory accesses across the optical network using a packet-switched, circuit-switched, or hybrid packet-and-circuit-switched approach. The novel memory controller is experimentally demonstrated to be compatible with existing processor-memory access protocols, with the memory controller acting as the optics-computing interface to render the optical network transparent. Additionally, the flexibility of the optical network enables additional performance benefits including increased memory bandwidth through optical multicasting. This optically-connected architecture can further enable more resilient memory system realizations by expanding on current error dectection and correction memory protocols. The integration of optics with memory technology constitutes a critical step for both optics and computing. The scalability challenges facing main memory systems today, especially concerning bandwidth and power consumption, complement well with the strengths of optical communications-based systems. Additionally, ongoing efforts focused on developing low-cost optical components and subsystems that are suitable for computing environments may benefit from the high-volume memory market. This work therefore takes the first step in merging the areas of optics and memory, developing the necessary architectures and protocols to interface the two technologies, and demonstrating potential benefits while identifying areas for future work. Future computing systems will undoubtedly benefit from this work through the deployment of high-performance, flexible, energy-efficient optically-connected memory architectures.

The push for higher levels of performance drives research and innovation in all areas of electronics. Thus far, shrinking circuit sizes and development of new material systems have satisfied this need. Continued scaling and material improvements have become increasingly difficult; simultaneously, more functionality is needed in smaller spaces. Advanced integration techniques provide a solution by engineering together previously incompatible systems. The fabrication of high-performance devices typically requires high temperature processing steps. Since fabrication occurs sequentially, the high temperature prevents the direct integration of two high-performance layers, as completed devices cannot withstand the processing temperatures of subsequent steps. There are significant challenges to integrating process-incompatible systems, and techniques such as wafer bonding, heteroepitaxial growth, and various thin film technologies have shown limited success. In this work, advanced integration is achieved through laser crystallization processes. Unique to laser methods is the ability to locally heat the surface of a material while keeping the underlying substrate at room temperature. This property allows for high performance electronic materials to be integrated with substrates of different functionalities. This thesis focuses on three key components for advanced integration: 1. Laser-crystallized electronic devices, 2. Relevant substrates for integration, and 3. The feasibility of integrating of laser-crystallized devices with low-temperature substrates. Two types of laser-crystallized devices are explored. Thin-film, laser-crystallized silicon transistors are fabricated at low-temperatures and exhibit high mobilities above 400 cm2 2/Vs. Vertical structure diodes built from laser-crystallized silicon outperformed epitaxially-grown diodes of the same geometry. Light emitting diode (LED) arrays are fabricated from compound semiconductor substrates and tested for display applications. These LED arrays are envisioned to sit underneath the laser-crystallized devices, enabling new applications where both high brightness and high performance transistors are needed. Substrates of low-κ dielectric material are also of interest, as they are widely used for their low capacitance properties. Preliminary results suggest that laser crystallization of silicon can be successfully performed on a low-κ dielectric. In addition to enabling new device architectures, it is important for laser crystallization methods to leave the underlying layers unaffected. Simulations of the laser irradiation process predict substrate temperatures to reach only 70C even when the surface reaches the melting temperature of silicon (1400C). Integration feasibility is further investigated with measurements on conventional front-end field effect transistors. When comparing properties from wafers with and without laser processing, no changes in transistor characteristics are observed. In all three components of work, proof-of-principle devices and concepts lay out the groundwork for future investigation. The developed technologies have promising applications in both the microelectronics and display industry. In particular, the integration of LEDs and laser-crystallized silicon enables a high-brightness microdisplay platform for head-mounted displays, pico projectors, and head-up displays.

In the power-starved wireless sensor node application, the main transceiver has to be duty-cycled to prolong the node battery lifetime. Wake-up is among the lowest power schemes to accomplish this; an always ON low-power receiver called the wake-up receiver is used to turn ON the main receiver when needed. In this thesis, we have demonstrated ultra-low-power wake-up by using through-air wireless ultrasound. We have achieved more than an order of magnitude reduction in wake-up receiver power consumption, compared to conventionally used radio frequencies. An ultra-low-power ultrasonic wake-up receiver IC was designed in a 65-nm CMOS process and has a power consumption of only 4.4 uW. For the proof-of-concept prototype demonstrated in this work, the digital back-end circuits were been implemented on a commercial FPGA. An ultrasound data network consisting of three receivers and one transmitter was set up in a lecture hall. For a transmit power of 27 uW, less than 10 % of the wake-up packets, at 1 pkt/s, were missed at each of the three receivers. All the system blocks: receiver IC, ultrasound communication channel and TX-RX transducer pair, were individually characterized in different environments to understand the interaction between the electrical and mechanical domains. Also presented are techniques for increasing the distance ranges of wireless ultrasound and communication schemes for extending the use of ultrasound to environments where line-of-sight communication is not possible.