Thesis (M.S.) Massachusetts Institute of Technology. Dept. of Electrical Engineering, 1952. / by Stanley H. Logue. / M.S.

abstract: Semiconductor memory is a key component of the computing systems. Beyond the conventional memory and data storage applications, in this dissertation, both mainstream and eNVM memory technologies are explored for radiation environment, hardware security system and machine learning applications. In the radiation environment, e.g. aerospace, the memory devices face different energetic particles. The strike of these energetic particles can generate electron-hole pairs (directly or indirectly) as they pass through the semiconductor device, resulting in photo-induced current, and may change the memory state. First, the trend of radiation effects of the mainstream memory technologies with technology node scaling is reviewed. Then, single event effects of the oxide based resistive switching random memory (RRAM), one of eNVM technologies, is investigated from the circuit-level to the system level. Physical Unclonable Function (PUF) has been widely investigated as a promising hardware security primitive, which employs the inherent randomness in a physical system (e.g. the intrinsic semiconductor manufacturing variability). In the dissertation, two RRAM-based PUF implementations are proposed for cryptographic key generation (weak PUF) and device authentication (strong PUF), respectively. The performance of the RRAM PUFs are evaluated with experiment and simulation. The impact of non-ideal circuit effects on the performance of the PUFs is also investigated and optimization strategies are proposed to solve the non-ideal effects. Besides, the security resistance against modeling and machine learning attacks is analyzed as well. Deep neural networks (DNNs) have shown remarkable improvements in various intelligent applications such as image classification, speech classification and object localization and detection. Increasing efforts have been devoted to develop hardware accelerators. In this dissertation, two types of compute-in-memory (CIM) based hardware accelerator designs with SRAM and eNVM technologies are proposed for two binary neural networks, i.e. hybrid BNN (HBNN) and XNOR-BNN, respectively, which are explored for the hardware resource-limited platforms, e.g. edge devices.. These designs feature with high the throughput, scalability, low latency and high energy efficiency. Finally, we have successfully taped-out and validated the proposed designs with SRAM technology in TSMC 65 nm. Overall, this dissertation paves the paths for memory technologies’ new applications towards the secure and energy-efficient artificial intelligence system. / Dissertation/Thesis / Doctoral Dissertation Electrical Engineering 2018

abstract: A human communications research project at Arizona State University aurally recorded the daily interactions of aware and consenting employees and their visiting clients at the Software Factory, a software engineering consulting team, over a three year period. The resulting dataset contains valuable insights on the communication networks that the participants formed however it is far too vast to be processed manually by researchers. In this work, digital signal processing techniques are employed to develop a software toolkit that can aid in estimating the observable networks contained in the Software Factory recordings. A four-step process is employed that starts with parsing available metadata to initially align the recordings followed by alignment estimation and correction. Once aligned, the recordings are processed for common signals that are detected across multiple participants’ recordings which serve as a proxy for conversations. Lastly, visualization tools are developed to graphically encode the estimated similarity measures to efficiently convey the observable network relationships to assist in future human communications research. / Dissertation/Thesis / Masters Thesis Electrical Engineering 2018

abstract: Articial Neural Network(ANN) has become a for-bearer in the field of Articial Intel- ligence. The innovations in ANN has led to ground breaking technological advances like self-driving vehicles,medical diagnosis,speech Processing,personal assistants and many more. These were inspired by evolution and working of our brains. Similar to how our brain evolved using a combination of epigenetics and live stimulus,ANN require training to learn patterns.The training usually requires a lot of computation and memory accesses. To realize these systems in real embedded hardware many Energy/Power/Performance issues needs to be solved. The purpose of this research is to focus on methods to study data movement requirement for generic Neural Net- work along with the energy associated with it and suggest some ways to improve the design.Many methods have suggested ways to optimize using mix of computation and data movement solutions without affecting task accuracy. But these methods lack a computation model to calculate the energy and depend on mere back of the envelope calculation. We realized that there is a need for a generic quantitative analysis for memory access energy which helps in better architectural exploration. We show that the present architectural tools are either incompatible or too slow and we need a better analytical method to estimate data movement energy. We also propose a simplistic yet effective approach that is robust and expandable by users to support various systems. / Dissertation/Thesis / Masters Thesis Electrical Engineering 2018

abstract: This work covers the design and implementation of a Parallel Doherty RF Power Amplifier in a GaN HEMT process for medium power macro-cell (16W) base station applications. This work improves the key parameters of a Doherty Power Amplifier including the peak and back-off efficiency, operational instantaneous bandwidth and output power by proposing a Parallel Doherty amplifier architecture. As there is a progression in the wireless communication systems from the first generation to the future 5G systems, there is ever increasing demand for higher data rates which means signals with higher peak-to-average power ratios (PAPR). The present modulation schemes require PAPRs close to 8-10dB. So, there is an urgent need to develop energy efficient power amplifiers that can transmit these high data rate signals. The Doherty Power Amplifier (DPA) is the most common PA architecture in the cellular infrastructure, as it achieves reasonably high back-off power levels with good efficiency. This work advances the DPA architecture by proposing a Parallel Doherty Power Amplifier to broaden the PAs instantaneous bandwidth, designed with frequency range of operation for 2.45 – 2.70 GHz to support WiMAX applications and future broadband signals. / Dissertation/Thesis / Masters Thesis Electrical Engineering 2018

abstract: Flexible hybrid electronics (FHE) is emerging as a promising solution to combine the benefits of printed electronics and silicon technology. FHE has many high-impact potential areas, such as wearable applications, health monitoring, and soft robotics, due to its physical advantages, which include light weight, low cost and the ability conform to different shapes. However, physical deformations that can occur in the field lead to significant testing and validation challenges. For example, designers have to ensure that FHE devices continue to meet specs even when the components experience stress due to bending. Hence, physical deformation, which is hard to emulate, has to be part of the test procedures developed for FHE devices. This paper is the first to analyze stress experience at different parts of FHE devices under different bending conditions. Then develop a novel methodology to maximize the test coverage with minimum number of text vectors with the help of a mixed integer linear programming formulation. / Dissertation/Thesis / Masters Thesis Electrical Engineering 2018

abstract: There is an increasing demand for fully integrated point-of-load (POL) isolated DC-DC converters that can provide an isolation barrier between the primary and the secondary side, while delivering a low ripple, low noise regulated voltage at their isolated sides to a high dynamic range, sensitive mixed signal devices, such as sensors, current-shunt-monitors and ADCs. For these applications, smaller system size and integration level is important because the whole system may need to fit to limited space. Traditional methods for providing isolated power are discrete solutions using bulky transformers. Miniaturization of isolated POL regulators is becoming highly desirable for low power applications. A fully integrated, low noise isolated point-of-load DC-DC converter for supply regulation of high dynamic range analog and mixed signal sensor signal-chains is presented. The isolated DC-DC converter utilizes an integrated planar air-core micro-transformer as a coupled resonator and isolation barrier and enables direct connection of low-voltage mixed signal circuits to higher supply rails. The air core transformer is driven at its primary resonant frequency of 100 MHz to achieve maximum power transfer. A mixed-signal perturb-and-observe based frequency search algorithm is developed to improve maximum power transfer efficiency by 60% across the isolation barrier compared to fixed driving frequency method. The isolated converter’s output ripple is reduced by utilizing spread spectrum clocking in the driver. An isolated PMOS LDO in the secondary side is used to suppress switching noise and ripple by 21dB. Conducted and radiated EMI distribution on the IC is measured by a set of integrated ring oscillator based noise sensors with -68dBm noise sensitivity. The proposed isolated converter achieves highest level of integration with respect to earlier reported integrated isolated converters, while providing 50V on-chip junction isolation without the need for extra silicon post-processing steps. / Dissertation/Thesis / Doctoral Dissertation Electrical Engineering 2018

abstract: Transmission line parameters play an important role in state estimation, dynamic line rating, and fault analysis. Because of this, several methods have been proposed in the literature for line parameter estimation, especially using synchrophasor data. However, success of most prior research has been demonstrated using purely synthetic data. A synthetic dataset does not have the problems encountered with real data, such as invariance of measurements and realistic field noise. Therefore, the algorithms developed using synthetic datasets may not be as effective when used in practice. On the other hand, the true values of the line parameters are unknown and therefore the algorithms cannot be directly implemented on real data. A multi-stage test procedure is developed in this work to circumvent this problem. In this thesis, two popular algorithms, namely, moving-window total least squares (MWTLS) and recursive Kalman filter (RKF) are applied on real data in multiple stages. In the first stage, the algorithms are tested on a purely synthetic dataset. This is followed by testing done on pseudo-synthetic datasets generated using real PMU data. In the final stage, the algorithms are implemented on the real PMU data obtained from a local utility. The results show that in the context of the given problem, RKF has better performance than MWTLS. Furthermore, to improve the performance of RKF on real data, ASPEN data are used to calculate the initial estimates. The estimation results show that the RKF algorithm can reliably estimate the sequence impedances, using ASPEN data as a starting condition. The estimation procedure is repeated over different time periods and the corresponding results are presented. Finally, the significance of data drop-outs and its impact on the use of parameter estimates for real-time power system applications, such as state estimation and dynamic line rating, is discussed. To address the problem (of data drop-outs), an auto regressive integrated moving average (ARIMA) model is implemented. The ability of this model to predict the variations in sequence impedances is demonstrated. / Dissertation/Thesis / Masters Thesis Electrical Engineering 2018

Tässä kandidaatintyössä suunniteltiin tehovahvistin, joka vahvistaa logiikkatasoisen signaalin 60 W tehoksi ultraäänilähettimelle. Suunnittelussa käytettiin apuna piirisimulaattoria. Suunnitellusta vahvistinpiiristä toteutettiin piirilevy EDA-ohjelmistolla. Rakennetun tehovahvistimen toimintaa tutkittiin mittaamalla jännitesignaaleja resistiivisten kuormien sekä ultraäänivahvistimen yli. / This bachelor’s thesis consists of the design process of an amplifier, which amplifies a logic level signal to 60 W power for ultrasonic transducer. Circuit simulator was used for designing the circuit. Circuit board was designed from designed amplifier circuit using EDA-software. Operation of the assembled power amplifier was studied by measuring voltage signals across resistive loads and ultrasonic transducer.

Recently with the advancement of solid state lighting and the application thereof to Visible Light Communications (VLC), the concept of Visible Light Positioning (VLP) has been targeted as a very attractive indoor positioning system (IPS) due to its ubiquity, directionality, spatial reuse, and relatively high modulation bandwidth. IPSs, in general, have 4 major components (1) a modulation, (2) a multiple access scheme, (3) a channel measurement, and (4) a positioning algorithm. A number of VLP approaches have been proposed in the literature and primarily focus on a fixed combination of these elements and moreover evaluate the quality of the contribution often by accuracy or precision alone. In this dissertation, we provide a novel two-phase indoor positioning algorithmic framework that is able to increase robustness when subject to insufficient anchor luminaries and also incorporate any combination of the four major IPS components. The first phase provides robust and timely albeit less accurate positioning proximity estimates without requiring more than a single luminary anchor using time division access to On Off Keying (OOK) modulated signals while the second phase provides a more accurate, conventional, positioning estimate approach using a novel geometric constrained triangulation algorithm based on angle of arrival (AoA) measurements. However, this approach is still an application of a specific combination of IPS components. To achieve a broader impact, the framework is employed on a collection of IPS component combinations ranging from (1) pulsed modulations to multicarrier modulations, (2) time, frequency, and code division multiple access, (3) received signal strength (RSS), time of flight (ToF), and AoA, as well as (4) trilateration and triangulation positioning algorithms. Results illustrate full room positioning coverage ranging with median accuracies ranging from 3.09 cm to 12.07 cm at 50% duty cycle illumination levels. The framework further allows for duty cycle variation to include dimming modulations and results range from 3.62 cm to 13.15 cm at 20% duty cycle while 2.06 cm to 8.44 cm at a 78% duty cycle. Testbed results reinforce this frameworks applicability. Lastly, a novel latency constrained optimization algorithm can be overlaid on the two phase framework to decide when to simply use the coarse estimate or when to expend more computational resources on a potentially more accurate fine estimate. The creation of the two phase framework enables robust, illumination, latency sensitive positioning with the ability to be applied within a vast array of system deployment constraints.