This thesis presents the design and implementation of a high-speed read-access STT MRAM. The proposed design includes a 2T1MTJ cell topology, along with two different read schemes: current-based and voltage-based. Compared to the conventional read scheme with 1T1MTJ cells, the proposed design is capable of reducing the loading on the read circuit to minimize the read access time. A complete STT MRAM test chip including the proposed and the conventional schemes was fabricated in 90nm CMOS technology. The 16kb test chip's measurement results confirm a read access time of 6ns and a write access time of 10ns. The read time is 25% faster than other works of similar array size published thus far, while the write time is able to match the fastest result.

This thesis presents the design and implementation of a high-speed read-access STT MRAM. The proposed design includes a 2T1MTJ cell topology, along with two different read schemes: current-based and voltage-based. Compared to the conventional read scheme with 1T1MTJ cells, the proposed design is capable of reducing the loading on the read circuit to minimize the read access time. A complete STT MRAM test chip including the proposed and the conventional schemes was fabricated in 90nm CMOS technology. The 16kb test chip's measurement results confirm a read access time of 6ns and a write access time of 10ns. The read time is 25% faster than other works of similar array size published thus far, while the write time is able to match the fastest result.