The <i>spin</i> of an electron has for long excited researchers both with respect to its fundamental physics and technological applications. Consequently, the traditional field driven switching of ferromagnets gave way for more scalable current driven switching based on the well-known spin transfer torque phenomenon. However, in the quest for better energy-efficiency, the manipulation of electron spin through pure voltage driven or voltage-assisted mechanisms are being intensely explored. In this research, we demonstrate that the very physics and the characteristics of such voltage driven devices enable interesting possibilities with respect to memory, neuromorphic and logic applications. We rely on the recent experimental demonstrations of two novel voltage effects on nano-magnets - the voltage controlled magnetic anisotropy (VCMA) and the pure voltage driven magneto-electric (ME) effect. Specifically, we propose in-situ, in-memory, vector logic operations by exploiting the voltage asymmetry and precessional switching dynamics of the VCMA effect to construct 'stateful' logic gates. Stateful logic are those in which the same device acts as a storage element and compute engine, simultaneously. In addition, we show that the pure voltage driven mono-domain switching and domain-wall motion of nano-magnets through the ME effect can be leveraged to construct neuro-mimetic devices exhibiting leaky-integrate-fire dynamics of biological neurons and as well as non-volatile synaptic elements. Further, we propose a voltage driven logic-device using the ME switching and demonstrate that the proposed logic-device can be used to construct a complete cascadable logic family including XNOR, IMP (implication), NAND and NOR gates. Additionally, we present an energy and area efficient content addressable memory using a logic compatible ME-XNOR device. The presented research shows that voltage driven switching can augment the very functionality and widen the application scope of spin based devices and circuits.

For many decades, the revolution in semiconductor industry has continuously been powered by the successful down scaling of complementary metal-oxide semiconductor (CMOS) technology to produce integrated circuits with improved performance at lower cost. However, current charge-based CMOS technology is already approaching physical limits and, thus, encounters a number of technological challenges. Spintronics is an emerging and rapidly evolving research field that has a great potential to overcome these challenges confronting CMOS by introducing the electron spin, in addition to electron charge, as an extra degree of freedom. Traditional spintronic devices are based on the alignment of spins in magnetic layers, manipulated by spin-polarized currents. Thus, employing the non-volatile nature of layer magnetization and its direction to represent the bit state, spintronics provides power-efficient devices that are attractive for memory and logic applications. Magnetoresistive random access memory (MRAM) is one of the most essential applications of spin based electronics, which has already been recognized as the leading candidate for future universal memory. MRAM cells use spin-based magnetic tunnel junctions (MTJs) as the fundamental storage blocks. These conventional MTJs employ the use of magnetic elements with a single axis of magnetization, which provide two resistance states, capable of storing one bit of information. Enhancing the memory density is one of the major challenges encountered by MRAM industry, as the straightforward approach of reducing the magnetic bit size is unfeasible with magnetic devices due to intrinsic superparamagnetism effects. In this thesis, we propose increasing the bit density in MRAM by implementing shape anisotropy induced multistate MTJs. By patterning the free ferromagnetic layer of MTJs in the shape of four intersecting ellipses we achieve four in-plane stable axes of magnetization, capable of providing eight resistance states in total, the switching between which is performed by spin-orbit torques (SOT) in spin Hall metals (SHM). We initially verify the proposed concept with micromagnetic simulations followed by fabrication and, consequent, room temperature characterization of the first experimental prototypes.

This thesis explores the use of 2D materials (graphene and hBN) for spintronics. Interest on these materials in spintronics arose from theoretical predictions of high spin filtering in out-of-plane transport through graphene and hBN sandwiched by ferromagnets. Similarly, 5-layer graphene was forecast to be a perfect spin filter. In the case of in-plane spin transport, graphene was expected to be an excellent material due to its low spin-orbit coupling and low number of defects. Although there already exist experimental works that attempted to explore the aforementioned predictions, they have failed so far to comply with the expected results. Earlier experimental works in graphene and hBN out-of-plane spin transport achieved low spin filtering on the order of a few percent; while spin relaxation parameters in graphene for in-plane spin transport remained one or two orders of magnitude below the predicted values. In the case of vertical devices, the failure to meet the theoretical expectations was attributed to the oxidation of the ferromagnets and the lack of an epitaxial interface between the later and the graphene or hBN. Similarly, the exact mechanisms that lead to high spin relaxation for in-plane spin transport in graphene are not completely understood, in part due to the low-quality of the explored devices. In this thesis we analyze new architectures and procedures that allowed us to fabricate ultraclean and oxidation-free interfaces between ferromagnets and graphene or hBN. In these devices we encountered negative and reversible magnetoresistance, that could not be explained with the previous theoretical models. We propose a new model based on a thorough characterization of the devices and well-known properties of graphene that were not taken into account in the previous model. We also employed a novel type of contact to graphene (1D-contacts) and applied it for the first time to achieve spin-injection in graphene. The main advantage of this type of contact is the full encapsulation of graphene with hBN, which leads to high quality graphene spintronic devices.

Magnetic biosensors detect biological targets through sensing the stray field of magnetic beads which label the targets. Commonly, magnetic biosensors employ the “sandwich” method to immobilize biological targets, i.e., the targets are sandwiched between a bio-functionalized sensor surface and bio-functionalized magnetic beads. This method has been used very successfully in different application, but its execution requires a rather elaborate procedure including several washing and incubation steps. This dissertation investigates a new magnetic biosensor concept, which enables a simple and effective detection of biological targets. The biosensor takes advantage of the size difference between bare magnetic beads and compounds of magnetic beads and biological targets. First, the detection of super-paramagnetic beads via magnetic tunnel junction (MTJ) sensors is implemented. Frequency modulation is used to enhance the signal-to-noise ratio, enabling the detection of a single magnetic bead. Second, the concept of the magnetic biosensor is investigated theoretically. The biosensor consists of an MTJ sensor, which detects the stray field of magnetic beads inside of a trap on top of the MTJ. A microwire between the trap and the MTJ is used to attract magnetic beads to the trapping well by applying a current to it. The MTJ sensor’s output depends on the number of beads inside the trap. If biological targets are in the sample solution, the beads will form bead compounds consisting of beads linked to the biological targets. Since bead compounds are larger than bare beads, the number of beads inside the trapping well will depend on the presence of biological targets. Hence, the output of the MTJ sensor will depend on the biological targets. The dependences of sensor signals on the sizes of the MTJ sensor, magnetic beads and biological targets are studied to find the optimum constellations for the detection of specific biological targets. The optimization is demonstrated for the detection of E. coli, and similar optimization processes can be performed for the detection of other biological targets. Third, we demonstrate the new magnetic biosensor concept using a mechanical trap capable of detecting nucleic acids via the size difference between bare magnetic beads and bead compounds. The bead compounds are formed through linking nonmagnetic beads of 1 µm in diameter and magnetic beads of 2.8 µm in diameter by the target nucleic acids. The purpose of the nonmagnetic beads is to increase the size of the compounds, since the nucleic acid is very small compared to the magnetic beads. Alternatively, smaller magnetic beads could be used but their detection would be more challenging. Finally, an enhanced version of the magnetic biosensor concept is developed using an electromagnetic trap for the detection of E. coli. The trap is formed by a current-carrying microwire that attracts magnetic beads into a virtual sensing space. As in the case of the mechanical trap, the sensor signal depends on the number of beads inside of the sensing space. The distance which magnetic beads can be detected from by the MTJ sensor defines the sensing space. The results showed that the output signal depends on the concentration of E. coli in the sample solution and that individual E. coli bacterium inside the sensing space could be detected using super-paramagnetic beads that are 2.8 µm in diameter. In summary, this dissertation investigates a new magnetic biosensor concept, which detects biological targets via the size difference between bare magnetic beads and compounds of magnetic beads and biological targets. The new method is extremely simple and enables the detection of biological targets in two simple steps and within a short time. The concept is demonstrated for the detection of nucleic acid and E. coli.

Internet of Things (IoT) is a network of devices that are connected through the Internet to exchange the data for intelligent applications. Though IoT devices provide several advantages to improve the quality of life, they also present challenges related to security. The security issues related to IoT devices include leakage of information through Differential Power Analysis (DPA) based side channel attacks, authentication, piracy, etc. DPA is a type of side-channel attack where the attacker monitors the power consumption of the device to guess the secret key stored in it. There are several countermeasures to overcome DPA attacks. However, most of the existing countermeasures consume high power which makes them not suitable to implement in power constraint devices. IoT devices are battery operated, hence it is important to investigate the methods to design energy-efficient and secure IoT devices not susceptible to DPA attacks. In this research, we have explored the usefulness of a novel computing platform called adiabatic logic, low-leakage FinFET devices and Magnetic Tunnel Junction (MTJ) Logic-in-Memory (LiM) architecture to design energy-efficient and DPA secure hardware. Further, we have also explored the usefulness of adiabatic logic in the design of energy-efficient and reliable Physically Unclonable Function (PUF) circuits to overcome the authentication and piracy issues in IoT devices. Adiabatic logic is a low-power circuit design technique to design energy-efficient hardware. Adiabatic logic has reduced dynamic switching energy loss due to the recycling of charge to the power clock. As the first contribution of this dissertation, we have proposed a novel DPA-resistant adiabatic logic family called Energy-Efficient Secure Positive Feedback Adiabatic Logic (EE-SPFAL). EE-SPFAL based circuits are energy-efficient compared to the conventional CMOS based design because of recycling the charge after every clock cycle. Further, EE-SPFAL based circuits consume uniform power irrespective of input data transition which makes them resilience against DPA attacks. Scaling of CMOS transistors have served the industry for more than 50 years in providing integrated circuits that are denser, and cheaper along with its high performance, and low power. However, scaling of the transistors leads to increase in leakage current. Increase in leakage current reduces the energy-efficiency of the computing circuits,and increases their vulnerability to DPA attack. Hence, it is important to investigate the crypto circuits in low leakage devices such as FinFET to make them energy-efficient and DPA resistant. In this dissertation, we have proposed a novel FinFET based Secure Adiabatic Logic (FinSAL) family. FinSAL based designs utilize the low-leakage FinFET device along with adiabatic logic principles to improve energy-efficiency along with its resistance against DPA attack. Recently, Magnetic Tunnel Junction (MTJ)/CMOS based Logic-in-Memory (LiM) circuits have been explored to design low-power non-volatile hardware. Some of the advantages of MTJ device include non-volatility, near-zero leakage power, high integration density and easy compatibility with CMOS devices. However, the differences in power consumption between the switching of MTJ devices increase the vulnerability of Differential Power Analysis (DPA) based side-channel attack. Further, the MTJ/CMOS hybrid logic circuits which require frequent switching of MTJs are not very energy-efficient due to the significant energy required to switch the MTJ devices. In the third contribution of this dissertation, we have investigated a novel approach of building cryptographic hardware in MTJ/CMOS circuits using Look-Up Table (LUT) based method where the data stored in MTJs are constant during the entire encryption/decryption operation. Currently, high supply voltage is required in both writing and sensing operations of hybrid MTJ/CMOS based LiM circuits which consumes a considerable amount of energy. In order to meet the power budget in low-power devices, it is important to investigate the novel design techniques to design ultra-low-power MTJ/CMOS circuits. In the fourth contribution of this dissertation, we have proposed a novel energy-efficient Secure MTJ/CMOS Logic (SMCL) family. The proposed SMCL logic family consumes uniform power irrespective of data transition in MTJ and more energy-efficient compared to the state-of-art MTJ/ CMOS designs by using charge sharing technique. The other important contribution of this dissertation is the design of reliable Physical Unclonable Function (PUF). Physically Unclonable Function (PUF) are circuits which are used to generate secret keys to avoid the piracy and device authentication problems. However, existing PUFs consume high power and they suffer from the problem of generating unreliable bits. This dissertation have addressed this issue in PUFs by designing a novel adiabatic logic based PUF. The time ramp voltages in adiabatic PUF is utilized to improve the reliability of the PUF along with its energy-efficiency. Reliability of the adiabatic logic based PUF proposed in this dissertation is tested through simulation based temperature variations and supply voltage variations.

Computer memories now play a key role in our everyday life given the increase in the number of connected smart devices and wearables. Recently post-CMOS memory technologies are gaining significant research attention along with the regular ones. Spin Transfer Torque Magnetoresistive RAM (STT-MRAM) is one such post-CMOS memory technology with a rapidly growing commercial interest and potential across diverse application platforms. Research has shown the ability of STT-MRAM to replace different levels of memory hierarchy as well. In brief, STT-MRAM possesses all the favorable properties of a universal memory technology. In this dissertation we have explored the roles of this emerging memory technology beyond traditional storage. The purpose is to enhance the overall performance of the application platform that STT-MRAM is a part of. The roles that we explored are computation and security. We have discussed how the intrinsic properties of STT-MRAM can be used for computation and authentication. The two properties that we are interested in are the dipolar coupling between the magnetic memory cells and the variations in the geometries of the memory cell. Our contributions here are a 22nm CMOS integrated STT-MRAM based logic-in-memory architecture and a geometric variation based STT-MRAM signature generation. In addition we have explored the device physics and the dynamics of STT-MRAM cells to propose a STT based clocking mechanism that is friendlier with the logic-in-memory setup. By investigating the logic layouts and propagation style in the architecture, we have also proposed different techniques that can improve the logic density and performance of the architecture.

This thesis presents the design and implementation of a high-speed read-access STT MRAM. The proposed design includes a 2T1MTJ cell topology, along with two different read schemes: current-based and voltage-based. Compared to the conventional read scheme with 1T1MTJ cells, the proposed design is capable of reducing the loading on the read circuit to minimize the read access time. A complete STT MRAM test chip including the proposed and the conventional schemes was fabricated in 90nm CMOS technology. The 16kb test chip's measurement results confirm a read access time of 6ns and a write access time of 10ns. The read time is 25% faster than other works of similar array size published thus far, while the write time is able to match the fastest result.

This thesis presents the design and implementation of a high-speed read-access STT MRAM. The proposed design includes a 2T1MTJ cell topology, along with two different read schemes: current-based and voltage-based. Compared to the conventional read scheme with 1T1MTJ cells, the proposed design is capable of reducing the loading on the read circuit to minimize the read access time. A complete STT MRAM test chip including the proposed and the conventional schemes was fabricated in 90nm CMOS technology. The 16kb test chip's measurement results confirm a read access time of 6ns and a write access time of 10ns. The read time is 25% faster than other works of similar array size published thus far, while the write time is able to match the fastest result.

This Master Thesis examines the possibility to apply a magnetometer developed by the Ångstöm space technology center to a small magnetic ground penetrating radar system with dimension in the order of one dm³. The magnetometer is broadband (DC-1GHz) and miniaturized. Loop antennas are used to transmit the signal.    A series of experiments have been performed in order to characterize the system, mainly examining the ability to determine distance to a target, using continuous sine wave signals and pulse trains. Standing wave patterns are formed between antenna and target and can be used for determining distance in the continuous case. When using a pulse train, the echo from the target could not be resolved using the current experiment set up, distance could therefore not be determined.

Darbe analizuojamos mobilių įrenginių programavimo priemonių ir universalios sąsajos skirtingiems modeliams sukūrimo galimybės. Išanalizuotos IntelliJ IDEA, Eclipse IDE, Python for S60 ir NetBeans IDE programavimo priemonės. Aprašyti programavimo įrankių veikimo bruožai, nustatytos programavimo priemonių galimybės, išvardinti jų privalumai ir trūkumai. Pagal gautus rezultatus pasirinktas NetBeans IDE programavimo įrankis ir juo naudojantis sukurta taikomoji aplikacija. Ji skirta vairavimo mokyklos veiklos procesų optimizavimui bei moksliniams tyrimams atlikti. Taikomoji aplikacija išbandyta skirtingose mobilių įrenginių platfromose. Eksperimentinis tyrimas parodo kurios aplikacijos funkcijos veikia neteisingai. Svarbiausios funkcijos ištaisytos, tačiau keletas neatitikimu negali būti pašalinti, tokie kaip duomenų atvaizdavimas. Nustatyta, kad šis trūkumas gali būti pašalintas tik vaizduojant duomenų lentelę horizontaliai. Eksperimentinis tyrimas parodo kelis universalios sąsajos aplikacijos kūrimo metodus. Be to darbe pateiktas pasiūlymas universalios sąsajos kūrimui naudoti UML diagramas. / The goals of this master’s work are analyzes tools for mobile devices programming and universal interface for different models creation opportunities. Also the paper analyzes Java ME, Visual Studio .NET, Python for S60, NetBeans IDE and BREW programming tools. Describe the features of the functioning of the programming tools, to set the programming options, listed the advantages and disadvantages. The best in this analyze was NetBeans IDE. There are created IS conceptual model of driving school and project of mobile software. According to the programming tools analyzes results and IS project was created new application. It is dedicated to improve driving school processes and make scientific research. Application was tested in different mobile platforms. The test shown application functions which works wrong. Most important functions fixed, but some of them can’t be fixed, such as displaying full table of content. This bug can be fixed only displaying table horizontally. This experimental work shows some methods of universal application creation. Also there is suggested how we can create universal application by using UML diagrams.