For many decades, the revolution in semiconductor industry has continuously been powered by the successful down scaling of complementary metal-oxide semiconductor (CMOS) technology to produce integrated circuits with improved performance at lower cost. However, current charge-based CMOS technology is already approaching physical limits and, thus, encounters a number of technological challenges. Spintronics is an emerging and rapidly evolving research field that has a great potential to overcome these challenges confronting CMOS by introducing the electron spin, in addition to electron charge, as an extra degree of freedom. Traditional spintronic devices are based on the alignment of spins in magnetic layers, manipulated by spin-polarized currents. Thus, employing the non-volatile nature of layer magnetization and its direction to represent the bit state, spintronics provides power-efficient devices that are attractive for memory and logic applications. Magnetoresistive random access memory (MRAM) is one of the most essential applications of spin based electronics, which has already been recognized as the leading candidate for future universal memory. MRAM cells use spin-based magnetic tunnel junctions (MTJs) as the fundamental storage blocks. These conventional MTJs employ the use of magnetic elements with a single axis of magnetization, which provide two resistance states, capable of storing one bit of information. Enhancing the memory density is one of the major challenges encountered by MRAM industry, as the straightforward approach of reducing the magnetic bit size is unfeasible with magnetic devices due to intrinsic superparamagnetism effects. In this thesis, we propose increasing the bit density in MRAM by implementing shape anisotropy induced multistate MTJs. By patterning the free ferromagnetic layer of MTJs in the shape of four intersecting ellipses we achieve four in-plane stable axes of magnetization, capable of providing eight resistance states in total, the switching between which is performed by spin-orbit torques (SOT) in spin Hall metals (SHM). We initially verify the proposed concept with micromagnetic simulations followed by fabrication and, consequent, room temperature characterization of the first experimental prototypes.

Dissertation (Ph.D.) -- University of Texas Southwestern Medical Center at Dallas, 2006. / Vita. Bibliography: p.156-190

In this work, two new spintronic memory cell structures are proposed. The first cell uses the diffusion of polarized spins into ferromagnets with perpendicular anisotropy to tilt their magnetization followed by their dipolar coupling to a fixed magnet (Bhowmik et al., 2014). The possibility of setting the magnetization to both stable magnetization states in a controlled manner using a similar concept remains unknown, but the proposed structure poses to be a solution to this difficulty. The second cell proposed takes advantage of the multiple stable magnetic states that exist in ferromagnets with configurational anisotropy and also uses spin torques to manipulate its magnetization. It utilizes a square-shaped ferromagnet whose stable magnetization has preferred directions along the diagonals of the square, giving four stable magnetic states allowing to use the structure as a multi-bit memory cell. Both devices use spin currents generated in heavy metals by the Spin Hall effect present in these materials. Among the advantages of the structures proposed are their inherent non-volatility and the fact that there is no need for applying external magnetic fields during their operation, which drastically improves the energy efficiency of the devices. Computational simulations using the Object Oriented Micromagnetic Framework (OOMMF) software package were performed to study the dynamics of the magnetization process in both structures and predict their behavior. Besides, we fabricated a 4-terminal memory cell with configurational anisotropy similar to the device proposed, and found four stable resistive states on the structure, proving the feasibility of this technology for implementation of high-density, non-volatile memory cells.

In this thesis, we develop a temperature-dependent homogenization technique and implement it into the meshfree particle method for nanoscale continuum simulations. As a hierarchical multiscale method, the nanoscale meshfree particle method is employed to model and simulate nanostructured materials and devices. Recently developed multiscale methods can overcome the limitations of both length and time scales that molecular dynamics has. However, multiscale methods have difficulties in investigating temperature-dependent physical phenomena since most homogenization techniques employed in continuum models have an assumption of zero temperature. A new homogenization technique, the temperature-related Cauchy-Born (TCB) rule, is proposed with the consideration of the free energy instead of the potential energy in this thesis. This technique is verified via stress analyses of several crystalline solids. The studies of material stability demonstrate the significance of temperature effects on nanostructured material stability. Since meshfree particle methods have advantages on simulating the problems involving extremely large deformations and moving boundaries, they become attractive options to be used in the hierarchical multiscale modeling to approximate a large number of atoms. In this thesis, a nanoscale meshfree particle method with the implementation of the developed homogenization technique, i.e. the TCB rule, is proposed. It is shown that numerical simulations in nanotechnology can be beneficial from this technique by saving a great amount of computer time. The nanoscale meshfree particle method is employed to investigate the crack propagation in a nanoplate with the development of cohesive zone model and a thermal-mechanical coupling model. In addition, the nanoscale meshfree particle method is simplified to successfully study mechanisms of nanotube-based memory cells.

京都大学 / 0048 / 新制・論文博士 / 博士(工学) / 乙第13015号 / 論工博第4140号 / 新制||工||1650(附属図書館) / 32943 / (主査)教授 斧 髙一, 教授 木村 健二, 教授 立花 明知 / 学位規則第4条第2項該当 / Doctor of Philosophy (Engineering) / Kyoto University / DFAM

Afin de permettre le développement de modèles manipulables par les concepteurs, il est nécessaire de pouvoir comprendre le fonctionnement des nanotubes, en particulier le transport des électrons et leurs propriétés électroniques. C’est dans ce contexte général que cette thèse s’intègre. Le travail a été mené sur quatre plans : développement de modèles permettant la description des phénomènes physiques importants au niveau des dispositifs, expertise sur le fonctionnement des nano-composants permettant de dégager les ordres de grandeurs pertinents pour les dispositifs, les contraintes, la pertinence de quelques procédés de fabrication (reproductibilité, taux de défauts, collection de caractéristiques mesurées et développement éventuel d'expériences spécifiques, expertise et conception des circuits innovatifs pour l’électronique numérique avec ces nano-composants. / This PhD work presents a computationally efficient physics-based compact model for the Schottky barrier (SB) carbon nanotube field-effect transistor (CNTFET). This compact model includes a new analytical formulation of the channel charge, taking into account the influence of the source and drain SBs. Compact model simulation results (I–V characteristic and channel density of charge) as well as Monte Carlo simulation results, which are provided by a recent work, will be given and compared to each other and also to experimental data to validate the used approximations. Good agreement is observed over a large range of gate and drain biases. Furthermore, a scaling study is presented to examine the impact of technological parameters on the device figure of merit. Then, for the assessment of the SB on circuit performances, traditional logical circuits are designed using the SB-CNTFET compact model, and results are compared with a conventional CNTFET with zero-SB height. Finally, exploiting the particular properties of SB-CNTFETs, a three-valued static memory that is suitable for high density integration is presented.

[EN] SRAM technology has traditionally been used to implement processor caches since it is the fastest existing RAM technology.However,one of the major drawbacks of this technology is its high energy consumption.To reduce this energy consumption modern processors mainly use two complementary techniques: i)low-power operating modes and ii)low-power memory technologies.The first technique allows the processor working at low clock frequencies and supply voltages.The main limitation of this technique is that manufacturing defects can significantly affect the reliability of SRAM cells when working these modes.The second technique brings alternative technologies such as eDRAM, which provides minimum area and power consumption.The main drawback of this memory technology is that reads are destructive and eDRAM cells work slower than SRAM ones. This thesis presents three main contributions regarding low-power caches and heterogeneous technologies: i)an study that identifies the optimal capacitance of eDRAM cells, ii)a novel cache design that tolerates the faults produced by SRAM cells in low-power modes, iii)a methodology that allows obtain the optimal operating frequency/voltage level when working with low-power modes. Regarding the first contribution,in this work SRAM and eDRAM technologies are combined to achieve a low-power fast cache that requires smaller area than conventional designs and that tolerates SRAM failures.First,this dissertation focuses on one of the main critical aspects of the design of heterogeneous caches:eDRAM cell capacitance.In this dissertation the optimal capacitance for an heterogeneous L1 data cache is identified by analyzing the compromise between performance and energy consumption.Experimental results show that an heterogeneous cache implemented with 10fF capacitors offers similar performance as a conventional SRAM cache while providing 55% energy savings and reducing by 29% the cache area. Regarding the second contribution,this thesis proposes a novel organization for a fault-tolerant heterogeneous cache.Currently,reducing the supply voltage is a mechanism widely used to reduce consumption and applies when the system workload activity decreases.However,SRAM cells cause different types of failures when the supply voltage is reduced and thus they limit the minimum operating voltage of the microprocessor. In the proposal,memory cells implemented with eDRAM technology serve as backup in case of failure of SRAM cells, because the correct operation of eDRAM cells is not affected by reduced voltages. The proposed architecture has two working modes: high-performance mode for supply voltages that do not induce SRAM cell failures, and low-power mode for those voltages that cause SRAM cell failures. In high-performance mode, the cache provides full capacity, which enables the processor to achieve its maximum performance. In low-power mode, the effective capacity of the cache is reduced because some of the eDRAM cells are dedicated to recover from SRAM failures. Experimental results show that the performance is scarcely reduced (e.g. less than 2.7% across all the studied benchmarks) with respect to an ideal SRAM cache without failures. Finally,this thesis proposes a methodology to find the optimal frequency/voltage level regarding energy consumption for the designed heterogeneous cache. For this purpose, first SRAM failure types and their probabilities are characterized.Then,the energy consumption of different frequency/voltage levels is evaluated when the system works in low-power mode.The study shows that, mainly due to the impact of SRAM failures on performance,the optimal combination of voltage and frequency from the energy point of view does not always correspond to the minimum voltage. / [ES] La tecnología SRAM se ha utilizado tradicionalmente para implementar las memorias cache debido a que es la tecnología de memoria RAM más rápida existente.Por contra,uno de los principales inconvenientes de esta tecnología es su elevado consumo energético.Para reducirlo los procesadores modernos suelen emplear dos técnicas complementarias:i) modos de funcionamiento de bajo consumo y ii)tecnologías de bajo consumo.La primeras técnica consiste en utilizar bajas frecuencias y voltajes de funcionamiento.La principal limitación de esta técnica es que los defectos de fabricación pueden afectar notablemente a la fiabilidad de las celdas SRAM en estos modos.La segunda técnica agrupa tecnologías alternativas como la eDRAM,que ofrece área y consumo mínimos.El inconveniente de esta tecnología es que las lecturas son destructivas y es más lenta que la SRAM. Esta tesis presenta tres contribuciones principales centradas en caches de bajo consumo y tecnologías heterogéneas: i)estudio de la capacitancia óptima de las celdas eDRAM, ii)diseño de una cache tolerante a fallos producidos en las celdas SRAM en modos de bajo consumo, iii)metodología para obtener la relación óptima entre voltaje y frecuencia en procesadores con modos de bajo consumo. Respecto a la primera contribución,en este trabajo se combinan las tecnologías SRAM y eDRAM para conseguir una memoria cache rápida, de bajo consumo, área reducida, y tolerante a los fallos inherentes a la tecnología SRAM.En primer lugar,esta disertación se centra en uno de los aspectos críticos de diseño de caches heterogéneas SRAM/eDRAM: la capacitancia de los condensadores implementados con tecnología eDRAM.En esta tesis se identifica la capacitancia óptima de una cache de datos L1 heterogénea mediante el estudio del compromiso entre prestaciones y consumo energético.Los resultados experimentales muestran que condensadores de 10fF ofrecen prestaciones similares a las de una cache SRAM convencional ahorrando un 55% de consumo y reduciendo un 29% el área ocupada por la cache. Respecto a la segunda contribución,esta tesis propone una organización de cache heterogénea tolerante a fallos.Actualmente,reducir el voltaje de alimentación es un mecanismo muy utilizado para reducir el consumo en condiciones de baja carga.Sin embargo,las celdas SRAM producen distintos tipos de fallos cuando se reduce el voltaje de alimentación y por tanto limitan el voltaje mínimo de funcionamiento del microprocesador. En la cache heterogénea propuesta,las celdas de memoria implementadas con tecnología eDRAM sirven de copia de seguridad en caso de fallo de las celdas SRAM, ya que el correcto funcionamiento de las celdas eDRAM no se ve afectado por tensiones reducidas.La arquitectura propuesta consta de dos modos de funcionamiento: high-performance mode para voltajes de alimentación que no inducen fallos en celdas implementadas en tecnología SRAM, y low-power mode para aquellos que sí lo hacen. En el modo high-performance mode,el procesador dispone de toda la capacidad de la cache.En el modo low-power mode se reduce la capacidad efectiva de la cache puesto que algunas de las celdas eDRAM se dedican a la recuperación de fallos de celdas SRAM.El estudio de prestaciones realizado muestra que éstas bajan hasta un máximo de 2.7% con respecto a una cache perfecta sin fallos. Finalmente, en esta tesis se propone una metodología para encontrar la relación óptima de voltaje/frecuencia con respecto al consumo energético sobre la cache heterogénea previamente diseñada. Para ello,primero se caracterizan los tipos de fallos SRAM y las probabilidades de fallo de los mismos.Después,se evalúa el consumo energético de diferentes combinaciones de voltaje/frecuencia cuando el sistema se encuentra en un modo de bajo consumo.El estudio muestra que la combinación óptima de voltaje y frecuencia desde el punto de vista energético no siempre corresponde al mínimo voltaje debido al imp / [CAT] La tecnologia SRAM s'ha utilitzat tradicionalment per a implementar les memòries cau degut a que és la tecnologia de memòria RAM més ràpida existent.Per contra, un dels principals inconvenients d'aquesta tecnologia és el seu elevat consum energètic.Per a reduir el consum els processadors moderns solen emprar dues tècniques complementàries: i)modes de funcionament de baix consum i ii)tecnologies de baix consum.La primera tècnica consisteix en utilitzar baixes freqüències i voltatges de funcionament.La principal limitació d'aquesta tècnica és que els defectes de fabricació poden afectar notablement a la fiabilitat de les cel·les SRAM en aquests modes.La segona tècnica agrupa tecnologies alternatives com la eDRAM, que ofereix àrea i consum mínims.L'inconvenient d'aquesta tecnologia és que les lectures són destructives i és més lenta que la SRAM. Aquesta tesi presenta tres contribucions principals centrades en caus de baix consum i tecnologies heterogènies: i)estudi de la capacitancia òptima de les cel·les eDRAM, ii)disseny d'una cau tolerant a fallades produïdes en les cel·les SRAM en modes de baix consum, iii)metodologia per a obtenir la relació òptima entre voltatge i freqüència en processadors amb modes de baix consum. Respecte a la primera contribució, en aquest treball es combinen les tecnologies SRAM i eDRAM per a aconseguir una memòria cau ràpida, de baix consum, àrea reduïda, i tolerant a les fallades inherents a la tecnologia SRAM.En primer lloc, aquesta dissertació se centra en un dels aspectes crítics de disseny de caus heterogènies: la capacitancia dels condensadors implementats amb tecnologia eDRAM.En aquesta dissertació s'identifica la capacitancia òptima d'una cache de dades L1 heterogènia mitjançant l'estudi del compromís entre prestacions i consum energètic.Els resultats experimentals mostren que condensadors de 10fF ofereixen prestacions similars a les d'una cau SRAM convencional estalviant un 55% de consum i reduint un 29% l'àrea ocupada per la cau. Respecte a la segona contribució, aquesta tesi proposa una organització de cau heterogènia tolerant a fallades.Actualment,reduir el voltatge d'alimentació és un mecanisme molt utilitzat per a reduir el consum en condicions de baixa càrrega.Per contra, les cel·les SRAM produeixen diferents tipus de fallades quan es redueix el voltatge d'alimentació i per tant limiten el voltatge mínim de funcionament del microprocessador. En la cau heterogènia proposta, les cel·les de memòria implementades amb tecnologia eDRAM serveixen de còpia de seguretat en cas de fallada de les cel·les SRAM, ja que el correcte funcionament de les cel·les eDRAM no es veu afectat per tensions reduïdes.L'arquitectura proposada consta de dues maneres de funcionament: high-performance mode per a voltatges d'alimentació que no indueixen fallades en cel·les implementades en tecnologia SRAM,i low-power mode per a aquells que sí ho fan.En el mode high-performance,el processador disposa de tota la capacitat de la cau.En el mode low-power es redueix la capacitat efectiva de la cau posat que algunes de les cel·les eDRAM es dediquen a la recuperació de fallades de cel·les SRAM.L'estudi de prestacions realitzat mostra que aquestes baixen fins a un màxim de 2.7% pel que fa a una cache perfecta sense fallades. Finalment,en aquesta tesi es proposa una metodologia per a trobar la relació òptima de voltatge/freqüència pel que fa al consum energètic sobre la cau heterogènia prèviament dissenyada.Per a açò,primer es caracteritzen els tipus de fallades SRAM i les probabilitats de fallada de les mateixes.Després,s'avalua el consum energètic de diferents combinacions de voltatge/freqüència quan el sistema es troba en un mode de baix consum.L'estudi mostra que la combinació òptima de voltatge i freqüència des del punt de vista energètic no sempre correspon al mínim voltatge degut a l'impacte de les fallades de SRAM en les pres / Lorente Garcés, VJ. (2015). Cache architectures based on heterogeneous technologies to deal with manufacturing errors [Tesis doctoral no publicada]. Universitat Politècnica de València. https://doi.org/10.4995/Thesis/10251/58428 / TESIS

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<div>Silicon based semiconductor technology is facing more and more challenges to continue the Moore's law due to its fundamental scaling limitations. To continue the pace of progress of device performance for both logic and memory devices, researchers are exploring new low-dimensional materials, e.g. nanowire, nanotube, graphene and hexagonal boron nitride. Transition metal dichalcogenides (TMDs) are attracted considerable attention due their atomically thin nature and proper bandgap at the initial study. Recently, more and more interesting properties are found in these materials, which will bring out more potential usefulness for electronic applications. Competing with the silicon device performance is not the only goal in the potential path finding of beyond silicon. Low-dimensional materials may have other outstanding performances as an alternative materials in many application realms. </div><div><br></div><div>This thesis explores the potential of TMD based devices in memory and logic applications. For the memory application, TMD based vertical devices are fully studied. Two-terminal vertical transition metal dichalcogenide (TMD) based memory selectors were firstly built and characterized, exhibiting better overall performance compared with some traditional selectors. Polymorphism is one of unique properties in TMD materials. 2D phase engineering in TMDs attracted great attention. While electric switching between semiconductor phase to metallic phase is the most desirable. In this thesis, electric field induced structural transition in MoTe₂ and Mo_1-xW_xTe₂ is firstly presented. Reproducible bipolar resistive random access (RRAM) behavior is observed in MoTe₂ and Mo_1-xW_xTe₂ based vertical devices. Direct confirmation of a phase transition from a 2H semiconductor to a distorted 2H_d metallic phase was obtained after applying an electric field. Set voltage is changed with flake thickness, and switching speed is less than 5 ns. Different from conventional RRAM devices based on ionic migration, the MoTe₂-based RRAMs offer intrinsically better reliability and control. In comparison to phase change memory (PCM)-based devices that operate based on a change between an amorphous and a crystalline structure, our MoTe₂-based RRAM devices allow faster switching due to a transition between two crystalline states. Moreover, utilization of atomically thin 2D materials allows for aggressive scaling and high-performance flexible electronics applications. Both of the studies shine lights on the new application in the memory field with two-dimensional materials.<br></div><div><br></div><div>For the logic application, the ultra thin body nature of TMDs allows for more aggressive scaling compared with bulk material - silicon. Two aspects of scaling properties in TMD based devices are discussed, channel length scaling and channel width scaling. A tunability of short channel effects in MoS₂ field effect transistor (FET) is reported. The electrical performance of MoS₂ flakes is governed by an unexpected dependence on the effective body thickness of the device which in turn depends on the amount of intercalated water molecules that exist in the layered structure. In particular, we observe that the doping stage of a MoS₂ FET strongly depends on the environment (air/vacuum). For the channel width scaling, the impact of edge states in three types of TMDs, metallic T_d-phase WTe₂ as well as semiconducting 2H-phase MoTe₂ and MoS₂ were explored, by patterning thin flakes into ribbons with varying channel widths. No obvious charge depletion at the edges is observed for any of these three materials, which is different from what has been observed in graphene nanoribbon devices. </div>

This paper describes various approaches to hardware testing semiconductor memory. We describe the priciple of basic memory types, the way which each of them stores information and their comunication protocol. Following part deals with common failures which may occur in the memory.  The section also describes the implementation of memory model and tester designed in VHDL language. It is possible to inject some errors into memory, which are later detected by the tester. The final section shows the response of tester to various error types according to used error detection method. The paper is especially focused on failure detection by variants of march test.