In order to carry out the complicated computation inside the high performance computing (HPC) systems, tens to hundreds of parallel processor chips and physical wires are required to be integrated inside the multi-chip package module (MCM). The physical wires considered as the electrical interconnects between the processor chips, however, have the challenges on placements and routings because of the unequal progress between the semiconductor and I/O size reductions. The primary goal of the research is to overcome package design challenges - providing a hybrid computing architecture with implemented 60 GHz antennas as the high efficient wireless interconnect which could generate over 10 Gbps bandwidth on the data transmissions. The dissertation is divided into three major parts. In the first part, two different performance metrics, power loss required to be recovered (PRE) and wireless link budget, on evaluating the antenna's system performance within the chip to chip wireless interconnect are introduced to address the design challenges and define the design goals. The second part contains the design concept, fabrication procedure and measurements of implemented 60 GHz broadband antenna in the application of multi-chip data transmissions. The developed antenna utilizes the periodically-patched artificial magnetic conductor (AMC) structure associated with the ground-shielded conductor in order to enhance the antenna's impedance matching bandwidth. The validation presents that over 10 GHz -10 dB S11 bandwidth which indicates the antenna's operating bandwidth and the horizontal data transmission capability which is required by planar type chip to chip interconnect can be achieved with the design concept. In order to reduce both PRE and wireless link budget numbers, a 60 GHz two-element array in the multi-chip communication is developed in the third part. The third section includes the combined-field analysis, the design concepts on two-element array and feeding circuitry. The simulation results agree with the predicted field analysis and demonstrate the 5dBi gain enhancement in the horizontal direction over a single 60 GHz AMC antenna to further reduce both PRE and wireless link budget numbers.

The demand of smaller and portable electronic devices has contributed to the realisation of compact embedded systems using PCB miniaturization techniques. The commercial market is faced with competition of handheld users’ devices in medical, communication and automotive industries which are smaller and lighter electronic devices. The possibilities of higher degree of integration in planar technology using cost effective electronic components has lead to different art of design and fabrication of compact units. In this work, a central station and a base station front-end with small form factor have been realized using commercial components on PCBs. These electronic compacts units were integrated in the IF-over-Fiber system architecture. The IF-over-Fiber architecture comprised of miniaturized electronic components for quadrature modulation and upconversion. The central station supports multi-Gbps data rate modulation formats in order to increase the spectral efficiency of the transmitted information. Multilevel modulation formats are considered spectrally efficient and can double the transmission capacity by transmitting more information in the amplitude, phase, polarization or a combination of all. The BS front-end comprises of the 60 GHz upconverter and a 60 GHz planar 2×2 microstrip antenna. The 10 GHz IF carrier allows an optical transmission with higher spectral efficiency in optical domain, as well as it is less susceptible to dispersion induced power fading inherent in optical fiber. Characterization of the designed central station and base station front-end through measurements are presented and discussed. The IF-over-Fiber system analysis is made for the 2 Gbps QPSK transmission with respect to error vector magnitude (EVM), eye and constellation diagrams.