Reed-Solomon (RS) codes are non-binary, forward error-correcting codes. The RS code is flexible, in that a code can be shortened, extended, interleaved and concatenated. This flexibility has made the RS code an important design block in communication system design and today the RS code is used within a large number of applications from data storage systems to space telecommunications. Implementations of the coding and decoding strategies have until recently been limited to software due to their high complexity, however, with recent advances in IC fabrication technology it has become possible for RS codecs to be implemented in hardware. A hardware implementation has a smaller silicon requirement, and makes the technology a more applicable solution for real-time applications. However, the problem for a hardware RS codec design solution today is the acknowledged lack of codec design experts. The work outlined in this document addresses this problem through the use of Design Automation (DA). This thesis describes a solution that employs a non-proprietary, technology independent generic VHDL core. The core is a single, self-contained generic circuit description, written entirely in standard synthesizable VHDL and can therefore be used by any synthesis tool on any CAD system to produce a gate-level description for any available technology. The core developed implements a bit-serial RS codec, using a time domain algorithm for encoding, and a frequency domain algorithm for decoding. Only a limited number of code description parameters are required to be entered into the core to produce a completed design in seconds. The results presented in the thesis illustrate in detail that the VHDL core generates efficient circuit architecture in terms of silicon area which are within I% of hand-crafted designs. Comparison of synthesized results to hand crafted designs are presented for all circuit structures from the simplest multiplier up to entire encoders and decoders. Technology independence has been illustrated through the use of synthesis of the core to a traditional semi-custom gate array, LSI Logic LCA300k series, and to a popular Xilinx FPGA. The actual circuit topology, and therefore the route of the circuit critical paths, for the gate array implementation are almost identical to the handcrafted design., since the VHDL core was based on experience gained in creating those circuits. The only differences are attributable to minor differences in synthesis cell libraries that affect the circuit topology in a small way and of course the resulting maximum clock rate which wi11 always be technology-dependent. Obviously, for other architectures, for example FPGAs, the actual route of the critical paths will also be different, but the technology dependence of the critical path is beyond the scope of this thesis.

The tremendous advancement in VLSI technologies in the past decade has fueled the need for intricate tradeoffs among speed, power dissipation and area. With gigahertz range microprocessors becoming commonplace, it is a typical design requirement to push the speed to its extreme while minimizing power dissipation and die area. Multipliers are critical components of many computational intensive circuits such as real time signal processing and arithmetic systems. The increasing demand in speed for floating-point co-processors, graphic processing units, CDMA systems and DSP chips has shaped the need for high-speed multipliers. The focus of our research for modern digital systems is two fold. The first one is to analyze a relatively unexplored logic style called MOS Current Mode Logic (MCML), which is a promising logic technique for the design of high performance arithmetic circuits with minimal power dissipation. The second one is to design high-speed arithmetic circuits, in particular, gigahertz-range multipliers that exploit the many attractive features of the MCML logic style. A small library of MCML gates that form the core components of the multiplier were designed and optimized for high-speed operation. The three 8-bit MCML multiplier architectures designed and simulated in TSMC 0.18 mm CMOS technology are: 3-2-tree architecture with ripple carry adder (Architecture I), 4-2-tree design with ripple carry adder (Architecture II) and 4-2-tree architecture with carry look-ahead adders (Architecture III). Architecture I operates with a maximum throughput of 4.76 GHz (4.76 Billion multiplications per second) and a latency of 3.78 ns. Architecture II has a maximum throughput of 3.3 GHz and a latency of 3 ns and Architecture III has a maximum throughput of 2 GHz and a latency of 3 ns. Architecture I achieves the highest throughput among the three multipliers, but it incurs the largest area and latency, in terms of clock cycle count as well as absolute delay. Although it is difficult to compare the speed of our multipliers with existing ones, due to the use of different technologies and different optimization goals, we believe our multipliers are among the fastest found in contemporary literature. / Master of Science

In order to carry out the complicated computation inside the high performance computing (HPC) systems, tens to hundreds of parallel processor chips and physical wires are required to be integrated inside the multi-chip package module (MCM). The physical wires considered as the electrical interconnects between the processor chips, however, have the challenges on placements and routings because of the unequal progress between the semiconductor and I/O size reductions. The primary goal of the research is to overcome package design challenges - providing a hybrid computing architecture with implemented 60 GHz antennas as the high efficient wireless interconnect which could generate over 10 Gbps bandwidth on the data transmissions. The dissertation is divided into three major parts. In the first part, two different performance metrics, power loss required to be recovered (PRE) and wireless link budget, on evaluating the antenna's system performance within the chip to chip wireless interconnect are introduced to address the design challenges and define the design goals. The second part contains the design concept, fabrication procedure and measurements of implemented 60 GHz broadband antenna in the application of multi-chip data transmissions. The developed antenna utilizes the periodically-patched artificial magnetic conductor (AMC) structure associated with the ground-shielded conductor in order to enhance the antenna's impedance matching bandwidth. The validation presents that over 10 GHz -10 dB S11 bandwidth which indicates the antenna's operating bandwidth and the horizontal data transmission capability which is required by planar type chip to chip interconnect can be achieved with the design concept. In order to reduce both PRE and wireless link budget numbers, a 60 GHz two-element array in the multi-chip communication is developed in the third part. The third section includes the combined-field analysis, the design concepts on two-element array and feeding circuitry. The simulation results agree with the predicted field analysis and demonstrate the 5dBi gain enhancement in the horizontal direction over a single 60 GHz AMC antenna to further reduce both PRE and wireless link budget numbers.