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Increased integration has resulted in the creation of so called System-onChip (SoC) devices. They ~embed all the essential parts of an advanced computer into a single silicon chip in order to achieve compactness, reduced material cost, higher performance and lower power consumption. An adverse consequence of this integration is that the external interfaces once observed dUring debugging are now inaccessible within the chip, no longer aiding development. Debug support brings back this otherwise lost visibility by providing an observation window into the SoC, the heart of the overall system. Integration now enables SoCs to contain more than one processor core. which has made existing debug support strategies ineffective at supporting application development. Moreover. these existing single processor oriented debugging strategies fail to align with the circuit reuse based methodologies necessary to rapidly_ create new SoCs.This thesis presents a novel debugging strategy that fully encompasses the requirements of SoC creation and application development. The strategy enables realisation of advanced embedded systems that incorporate complex SoCs; devices containing multiple processor cores and other active cores. It achieves these advantages through a package of novel contributions.

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Organic solar cells (OSCs) have attracted a significant attention during the last decade due to their simple processability on a flexible substrate as well as scope for large-scale production using role to role technique. Improving the performance of the organic solar cells and their lifetime stability are one of the main challenges faced by researchers in this field. In this thesis, work has been carried out using a blend of Poly(3-hexylthiophene-2,5-diyl) (P3HT) and [6,6]-Phenyl C61 butyric acid methyl ester (PCBM) as an active layer in the ratio of (1:1) (P3HT:PCBM). The efficiency and stability of P3HT:PCBM-based solar cells have been examined using different methods and employing novel materials such asl-[N-(2- ethoxyethyl) pent-4-ynamide] -8 (11), 15 (18), 22 (25) - tris -{2-[2-(2-ethoxyethoxy) ethoxy] -l-[2-((2- ethoxyethoxy) - ethoxy) methyl] ethyloxy] phthalocyaninato zinc (II) (ZnPc) to construct a ternary hybrid as the active layer. Controlling the morphology and crystallinity of P3HT:PCBM active layer was carried out using different solvents including chloroform (CF), chlorobenzene (CB) and dichlorobenzene (DCB) and their co-solvents in the ratio of (1:1) to dissolve the P3HT:PCBM blend. Optimum morphology and crystallinity were achieved using a co-solvent made of CB:CF with the obtained solar cell exhibiting the highest performance with PCE reaching 2.73% among other devices prepared using different solvents. Further device performance improvement was observed through optimization of active layer thickness with studied thickness falling in range 65-266 nm. Measurements of the PV characteristics of the investigated OSC devices have revealed optimum performance when active layer thickness was 95 nm with PCE=3.846%. The stability of the P3HT:PCBM-based devices on optimisation of the active layer thickness has shown a decrease in PCE of about 71% over a period of 41 days. Furthermore, P3HT has been blended with different fullerene derivatives (PC60BM, PC61BM, PC70BM and PC71BM) and the active layers were processed using the optimum solvent as well as optimum film’s thickness.

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The major part of the work described in the thesis is a study of a novel technique for the demodulation of two level phase shift keyed signals. Its advantage over conventional coherent demodulation methods is that it uses a free running oscillator as the local oscillator in the receiver, which is not locked to the transmitted carrier signal. Thus this novel system does not require the complex synchronisation techniques used in conventional phase shift keyed demodulators. This new demodulator like conventional coherent demodulators has not got the fixed speed disadvantage of differential phase shift keying. This new demodulator also referred to as a Quasi-Coherent demodulator has been characterised both theoretically and experimentally and compared with conventional coherent and differential phase shift-keyed systems. The possibility of extending this technique to multiphase phase shift keyed system is also discussed. The performance of a multilevel coherent phase shift keyed system in the presence of interference can be predicted by computing the exact mathematical equation for the error rate. In the thesis an approximate, but quick and simple method has been developed to, predict the performance of multilevel coherent phase shift keyed system from the well known result of a two level coherent phase shift keyed system. In all the interference analysis so far done by other authors, it is assumed that the reference at the receiver is coherent with the received signal. However, it is evident that in the presence of a strong interference, a phase locked loop derived reference will in general be coherent with the composite signal (i.e. signal plus interference plus noise) and not with the signal as assumed by previous authors. The effect of such a reference i.e. coherent with the composite signal on the performance of a two level system has been discussed fully in chapter four. The performance of a digital system also depends on the receiving filter characteristic and on the sampling jitter that is inevitably present in the sampling pulse in the decision circuitry of the receiver. The effect of these two factors on the performance of a two level coherent phase shift keyed system has been fully discussed in chapter five..

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Conventional pseudomorphic High Electron Mobility Transistor (pHEMTs) with lattice-matched InGaAs/InAlAs/InP structures exhibit high mobility and saturation velocity, and are hence attractive for the fabrication of three-terminal low noise and high frequency devices, which operate at room temperature. The major drawbacks of conventional pHEMT devices are the very low breakdown voltage (< 2 V) and the very high gate leakage current (~ 1 mA/mm), which degrade device, performance especially in MMIC LNAs. These drawbacks are caused by the impact ionization in the low band gap, i.e. the InxGa(1-x)As (x = 0.53 or 0.7) channel material plus the contribution of other parts of the epitaxial structure. The capability to achieve higher frequency operation is also hindered in conventional InGaAs/InAlAs/InP pHEMTs, due to the standard 1 μm flat gate length technology used. A key challenge in solving these issues is the optimization of the InGaAs/InAlAs epilayer structure through bandgap engineering, without affecting the device RF characteristics. A related challenge is the fabrication of sub-micron gate length devices using I-line optical lithography, which is more cost-effective, compared to the use of e-Beam lithography. The main goal for this research involves a radical departure from the conventional InGaAs/InAlAs/InP pHEMT structures by designing new and advanced epilayer structures, which significantly improves the performance of conventional low-noise pHEMT devices, and at the same time preserves the RF characteristics. To achieve this, modified epilayer structures were fabricated and characterized, including solving the standard 1 μm gate length processing issue. DC and RF results are then carefully analysed, and compared with those of the conventional pHEMT. Optimization of the submicron T-gate length process is then performed, by introducing a new technique to further scale-down the bottom gate opening. A new material, SoG, is also explored to simplify the submicron process flow even further. The results of this work show outstanding performance compared to the conventional pHEMT. The breakdown voltage and gate current leakage are significantly improved, by ≥ 70 % and ≥ 90 % respectively, with no detrimental effect on the RF characteristics, while the new technique of the submicron process shows a 58 % increase in fT, and 33 % increase in fmax. The SoG material shows suitability for use in a soft-reflow process, but due to some constraints, its development is left as future work; however, at present it could be used for passivation and production of capacitor dielectrics. The success of the modification and optimisation of the InGaAs/InAlAs material system, coupled with the gate length reduction into sub-μm regime enable high breakdown and ultra-high speed low noise devices to be fabricated, especially for low-noise amplifiers (LNAs) and low-noise receivers operating in the microwave and millimetre wave regime.