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No description available.

No description available.

No description available.

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Modern Field-Programmable Gate Arrays (FPGAs) are no longer used to implement small “glue logic” circuitries. The high-density of reconfigurable logic resources in today’s FPGAs enable the implementation of large systems in a single chip. FPGAs are highly flexible devices; their functionality can be altered by simply loading a new binary file in their configuration memory. While the flexibility of FPGAs is comparable to General-Purpose Processors (GPPs), in the sense that different functions can be performed using the same hardware, the performance gain that can be achieved using FPGAs can be orders of magnitudes higher as FPGAs offer the ability for customisation of parallel computational architectures. Dynamic Partial Reconfiguration (DPR) allows for changing the functionality of certain blocks on the chip while the rest of the FPGA is operational. DPR has sparked the interest of researchers to explore new computational platforms where computational tasks are off-loaded from a main CPU to be executed using dedicated reconfigurable hardware accelerators configured on demand at run-time. By having a battery of custom accelerators which can be swapped in and out of the FPGA at runtime, a higher computational density can be achieved compared to static systems where the accelerators are bound to fixed locations within the chip. Furthermore, the ability of relocating these accelerators across several locations on the chip allows for the implementation of adaptive systems which can mitigate emerging faults in the FPGA chip when operating in harsh environments. By porting the appropriate fault mitigation techniques in such computational platforms, the advantages of FPGAs can be harnessed in different applications in space and military electronics where FPGAs are usually seen as unreliable devices due to their sensitivity to radiation and extreme environmental conditions. In light of the above, this thesis investigates the deployment of DPR as: 1) a method for enhancing performance by efficient exploitation of the FPGA resources, and 2) a method for enhancing the reliability of systems intended to operate in harsh environments. Achieving optimal performance in such systems requires an efficient internal configuration management system to manage the reconfiguration and execution of the reconfigurable modules in the FPGA. In addition, the system needs to support “fault-resilience” features by integrating parameterisable fault detection and recovery capabilities to meet the reliability standard of fault-tolerant applications. This thesis addresses all the design and implementation aspects of an Internal Configuration Manger (ICM) which supports a novel bitstream relocation model to enable the placement of relocatable accelerators across several locations on the FPGA chip. In addition to supporting all the configuration capabilities required to implement a Reconfigurable Operating System (ROS), the proposed ICM also supports the novel multiple-clone configuration technique which allows for cloning several instances of the same hardware accelerator at the same time resulting in much shorter configuration time compared to traditional configuration techniques. A faulttolerant (FT) version of the proposed ICM which supports a comprehensive faultrecovery scheme is also introduced in this thesis. The proposed FT-ICM is designed with a much smaller area footprint compared to Triple Modular Redundancy (TMR) hardening techniques while keeping a comparable level of fault-resilience. The capabilities of the proposed ICM system are demonstrated with two novel applications. The first application demonstrates a proof-of-concept reliable FPGA server solution used for executing encryption/decryption queries. The proposed server deploys bitstream relocation and modular redundancy to mitigate both permanent and transient faults in the device. It also deploys a novel Built-In Self- Test (BIST) diagnosis scheme, specifically designed to detect emerging permanent faults in the system at run-time. The second application is a data mining application where DPR is used to increase the computational density of a system used to implement the Frequent Itemset Mining (FIM) problem.

The transform-quantisation stage is one of the most complex operations in the state-of-the-art High Efficiency Video Coding (HEVC) standard, accounting for 11–41% share of the encoding complexity. This study aims to reduce its complexity, making it suitable for dedicated hardware accelerated architectures. Adopted methods include multiplier-free approach, Multiple-Constant Multiplication architectural designs, and exploiting useful properties of the well-known Discrete Cosine Transform. Besides, an approximation scheme was introduced to represent the original HEVC transform and quantisation matrix elements with more hardware-friendly integers. Out of several derived approximation alternatives, an approximated transform matrix (T16) and its downscaled version (ST16) were further evaluated. An approximated quantisation multipliers matrix (Q) and its combination with one transform matrix (ST16 + Q) were also assessed in HEVC reference software, HM-13.0, using test video sequences of High Definition (HD) quality or higher. Their hardware architectures were designed in IEEE-VHDL language targeting a Xilinx Virtex-6 Field Programmable Gate Array technology to estimate resource savings over original HEVC transform and quantisation. T16, ST16, Q, and ST16 + Q approximated transform or/and quantisation matrices provided average Bjøntegaard-Delta bitrate differences of 1.7%, 1.7%, 0.0%, and 1.7%, respectively, in entertainment scenario and 0.7%, 0.7%, -0.1%, and 0.7%, respectively, in interactive scenario against HEVC. Conversely, around 16.9%, 20.8%, 21.2%, and 25.9% hardware savings, respectively, were attained in the number of Virtex-6 slices compared with HEVC transform or/and quantisation. The developed architecture designs achieved a 200 MHz operating frequency, enabling them to support the encoding of Quad Full HD (3840 × 2160) videos at 60 frames per second. Comparing T16 and ST16 with similar designs in the literature yields better hardware efficiency measures (0.0687 and 0.0721, respectively, in mega sample/second/slice). The presented approximated transform and quantisation matrices may be applicable in a complexity-reduced HEVC encoding on hardware platforms with non-detrimental coding performance degradations.

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