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Continued technology scaling on integrated circuits (IC) resulted in various benefits towards modern lifestyle. Smaller ICs made it possible to have daily-use devices at a small size and lower price. However, higher wear-out, stress effects and varied operating environment contributed towards shorter and severely limited lifetime. A possible solution to alleviate this problem is to introduce fault tolerance in the system that provides resilient towards the faults normally occur due to these effects. The main challenge here is to provide adequate increment towards reliability without imposing much overhead. To this end, this thesis presents several hardware and software approaches that improve the reliability of a system and also provide resilience towards transient and permanent faults. We observed that the multiple-faults aware placement strategy improves the lifetime reliability of digital circuits by lowering the error rate. We proposed several improvements in the multiple-faults aware placement strategy to achieve faster processing and higher reliability. These improvements are classified as hardware level approaches to achieve fault tolerance towards multiple faults in digital circuits. An analytical method is proposed using the Signal Probability Reliability Analysis (SPRA) that overcomes the issue of long simulation time for profiling pairs of cells/ gates. This method runs with one order magnitude faster than the original simulation approach. We also proposed the use of Hill Climbing strategy after Simulated Annealing to reduce the observed wire length in the original design. Experimental results show that this method can reduce the wire length up to 61%. We also proposed a novel optimisation algorithm to reduce the error rate by smartly manipulating the available spaces to separate the 'bad pairs' in the circuit. We investigated on the level of 'bad pair' considered in the optimisation algorithm. We found that with two categories of 'bad pairs', the error rate reduces up to 23% with little simulation time overhead. Checkpointing has been used over decades as one of primary software level approach for mitigating the effect of transient faults in a system. We studied the effectiveness of checkpointing in the view of lifetime reliability of a system than merely providing fault tolerance. Here, we proposed a novel checkpointing mechanism, namely, Lifetime Reliability-Aware Checkpointing Mechanism (LRAC), that is capable of not only tolerating transient fault but also migrating the task to a spare host whenever a permanent fault occurs or is expected to occur. We observed that this incurs approximately 12% time overhead, only during the occurrences of faults, even when the fault rate is as high as 10-3. However, this approach does not fail to meet the hard deadline of the tasks being executed.

This thesis presents a practical scenario for asynchronous logic implementation that would benefit the modern Field-Programmable Gate Arrays (FPGAs) technology in improving reliability. A method based on Asynchronously-Assisted Logic (AAL) blocks is proposed here in order to provide the right degree of variation tolerance, preserve as much of the traditional FPGAs structure as possible, and make use of asynchrony only when necessary or beneficial for functionality. The newly proposed AAL introduces extra underlying hard-blocks that support asynchronous interaction only when needed and at minimum overhead. This has the potential to avoid the obstacles to the progress of asynchronous designs, particularly in terms of area and power overheads. The proposed approach provides a solution that is complementary to existing variation tolerance techniques such as the late-binding technique, but improves the reliability of the system as well as reducing the design’s margin headroom when implemented on programmable logic devices (PLDs) or FPGAs. The proposed method suggests the deployment of configurable AAL blocks to reinforce only the variation-critical paths (VCPs) with the help of variation maps, rather than re-mapping and re-routing. The layout level results for this method's worst case increase in the CLB’s overall size only of 6.3%. The proposed strategy retains the structure of the global interconnect resources that occupy the lion’s share of the modern FPGA’s soft fabric, and yet permits the dual-rail iv completion-detection (DR-CD) protocol without the need to globally double the interconnect resources. Simulation results of global and interconnect voltage variations demonstrate the robustness of the method.

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This Thesis investigates formal models of concurrency that are often used in the process of the design of asynchronous circuits, namely transition systems and Petri nets. The aim of the Thesis is to relate various classes of transition systems and nets, so that different models can be used at different design stages. We characterise three classes of transition systems: the sequential Semi-elementary Transition Systems, and two classes of step transition systems, where arcs are labelled by sets of concurrently executed events: TSENI and TSENIapost Transition Systems. All three classes can be employed to describe the behaviour of safe Petri nets used in circuit design. Semi-elementary Transition Systems are generated by Semi-elementary Net Systems, which are basically Elementary Net Systems with added self-loops. TSENI (TSENIapost ) Transition Systems are step transition systems generated by Elementary Net Systems with Inhibitor Arcs executed according to the a- priori (resp. a-posteriori) semantics, and called ENI-systems (resp. ENIapost -systems). The relationship between each class of transition systems and nets is established via the notion of a region in the process of solving the synthesis problem for the appropriate class of nets. The Thesis compares the three classes of transition systems and gives examples of their use in the specification of asynchronous circuits behaviour.

Advances in hardware technologies combined with decreased costs have started a trend towards massively parallel architectures that utilise commodity components. It is thought unreasonable to expect software developers to manage the high degree of parallelism that is made available by these architectures. This thesis argues that a new programming model is essential for the development of parallel applications and presents a model which embraces the notions of object-orientation and implicit identification of parallelism. The new model allows software engineers to concentrate on development issues, using the object-oriented paradigm, whilst being freed from the burden of explicitly managing parallel activity. To support the programming model, the semantics of an execution model are defined and implemented as part of a run-time support system for object-oriented parallel applications. Details of the novel techniques from the run-time system, in the areas of lazy task creation and object-based, distributed shared memory, are presented. The tasklet construct for representing potentially parallel computation is introduced and further developed by this thesis. Three caching techniques that take advantage of memory access patterns exhibited in object-oriented applications are explored. Finally, the performance characteristics of the introduced run-time techniques are analysed through a number of benchmark applications.

In this thesis I shall examine the relationship between computers and the main users of computers in Lycees in Turkey in order to create a model of computer use in Turkey. Systems theory is used to define the sort of model or picture of users that a decision maker needs in order to provide a formal means of incorporating users and their needs into the system. Data are gathered and combined into a rich picture of the users. The 'soft' systems methodology developed by Checkland is used to test the rich picture and link it with monitoring of computer effectiveness in schools. Application of the Checkland methodology is a crucial step which shifted the emphasis of the project from qualitative to conceptual modelling. The methods of data collection and the results are described as the user survey. The following techniques are used: questionnaires, and semi-structured interviews. The data gathered by those methods presented a consistent picture in which the nature of the users' work, i.e. teachers, students, was the dominant influence on using computers in their learning and teaching. Application of the Checkland Methodology and the conceptual models derived from it are described as the systems study. A detailed description of the use of computers in mathematics is necessary in order to generate performance criteria. In addition, the rich picture from the user survey is found to be a fair representation of reality. Comparisons of each model with real world dynamism are undertaken. The comparisons indicate there are appreciable differences. Some implications of the study's findings are presented.

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