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Technology scaling of CMOS devices has made the integrated circuits vulnerable to single event radiation effects. Scaling of CMOS Static RAM (SRAM) has led to denser packing architectures by reducing the size and spacing of diffusion nodes. However, this trend has led to the increase in charge collection and sharing effects between devices during an ion strike, making the circuit even more vulnerable to a specific single event effect called the single event multiple-node upset (SEMU). In nanometer technologies, SEMU can easily disrupt the data stored in the memory and can be more hazardous than a single event single-node upset. During the last decade, most of the research efforts were mainly focused on improving the single event single-node upset tolerance of SRAM cells by using novel circuit techniques, but recent studies relating to angular radiation sensitivity has revealed the importance of SEMU and Multi Bit Upset (MBU) tolerance for SRAM cells. The research focuses on improving SEMU tolerance of CMOS SRAM cells by using novel circuit and layout level techniques. A novel SRAM cell circuit & layout technique is proposed to improve the SEMU tolerance of 6T SRAM cells with decreasing feature size, making it an ideal candidate for future technologies. The layout is based on strategically positioning diffusion nodes in such a way as to provide charge cancellation among nodes during SEMU radiation strikes, instead of charge build-up. The new design & layout technique can improve the SEMU tolerance levels by up to 20 times without sacrificing on area overhead and hence is suitable for high density SRAM designs in commercial applications. Finally, laser testing of SRAM based configuration memory of a Xilinx Virtex-5 FPGA is performed to analyze the behavior of SRAM based systems towards radiation strikes.

Indiana University-Purdue University Indianapolis (IUPUI) / In this thesis, we investigated the 7 nm FinFET technology for its delay-power product performance. In our study, we explored the ASAP7 library from Arizona State University, developed in collaboration with ARM Holdings. The FinFET technology was chosen since it has a subthreshold slope of 60mV/decade that enables cells to function at 0.7V supply voltage at the nominal corner. An emphasis was focused on characterizing the Non-Ideal effects, delay variation, and power for the FinFET device. An exhaustive analysis of the INVx1 delay variation for different operating conditions was also included, to assess the robustness. The 7nm FinFET device was then employed into 6T SRAM cells and 16 function ALU. The SRAM cells were approached with advanced multi-corner stability evaluation. The system-level architecture of the ALU has demonstrated an ultra-low power system operating at 1 GHz clock frequency.