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Wai-Tung Chung. / Thesis (M.Phil.)--Chinese University of Hong Kong, 1994. / Includes bibliographical references (leaves 102-104). / Chapter 1. --- Introduction --- p.1 / Chapter 1.1 --- Central Processing Unit innovation / Chapter 1.2 --- Long Instruction Word computer / Chapter 1.3 --- Prior attempts / Chapter 2. --- The new architecture --- p.11 / Chapter 2.1 --- The triple-instruction word / Chapter 2.2 --- Functional view of the architecture / Chapter 2.3 --- Inter-functional units synchronization / Chapter 2.4 --- Instruction set design / Chapter 2.5 --- Special features / Chapter 3. --- Simulation of the architecture --- p.39 / Chapter 3.1 --- Computer architecture simulation / Chapter 3.2 --- The simulation language used: APL / Chapter 3.3 --- Simulation environment / Chapter 3.4 --- Simulation design / Chapter 3.5 --- The micro-architecture / Chapter 3.6 --- Implementation details / Chapter 4. --- The supporting environment --- p.53 / Chapter 4.1 --- The environment / Chapter 4.2 --- The Pseudo-machine configuration / Chapter 4.3 --- Assembly language description / Chapter 4.4 --- Details of the utilities / Chapter 5. --- Evaluation --- p.53 / Chapter 5.1 --- Case Study / Chapter 5.2 --- Results and comparison / Chapter 5.3 --- Summary / Chapter 6. --- Discussion and conclusion --- p.96 / Chapter 6.1 --- The triple-instruction computer / Chapter 6.2 --- Use of APL for architectural simulation / Chapter 6.3 --- Further considerations / Chapter 7. --- References --- p.81 / Chapter 8. --- Appendix I: Program listing for the TIC simulator / Chapter 9. --- Appendix II: Screen dump of the simulation runs

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A methodology for the automatic translation of a Hardware Description Language (HDL) formulation of a VLSI system to a structured array-type of target realization is the subject of this investigation. A particular combination of input HDL and target technology has been implemented as part of the exercise, and a detailed evaluation of the result is presented. The HDL used in the study is AHPL, a synchronous clock-mode language which accepts the description of the hardware at Register Transfer Level. The target technology selected is Storage Logic Array (SLA), an evolution of PLA concept. Use of the SLA has a distinct advantage, notably in the ability to sidestep the interconnection routing problem, an expensive and time-consuming process in normal IC design. Over the past years, an enormous amount of effort has gone into generation of layout from an interconnection list. This conventional approach seems to complicate the placement and routing processes in later stages. In this research project the major emphasis has therefore been on extracting relevant global information from the higher-level description to guide the subsequent placement and routing algorithms. This effectively generates the lower-level layout directly from higher-level description. A special version of AHPL compiler (stage 3) has been developed as part of the project. The SLA data structure formats and the implementation of the Data and Control Sections of the target are described in detail. Also the evaluation and possibilities for future research are discussed.

Thesis (B.S.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1979. / MICROFICHE COPY AVAILABLE IN ARCHIVES AND ENGINEERING. / Includes bibliographical references. / by Jeremy Howard Nussbaum. / B.S.